Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

split ports for port property json file and add sec option for formal… #290

Merged
merged 1 commit into from
Mar 26, 2024

Conversation

BessonThierry
Copy link
Collaborator

This PR addresses two different unrelated improvements :

  1. improves port property json file generation by splitting ports and associate correct properties to each of them. It adds also "top" module name info.
  2. introduce the first "sec" sequential formal verification mechanism which is triggered with the -sec option in "synth_rs". The new code does not interfer with the official flow so it is safe.

@BessonThierry BessonThierry self-assigned this Mar 26, 2024
@alaindargelas alaindargelas merged commit dca23bc into os-fpga:main Mar 26, 2024
1 of 2 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants