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clean-up fix for EDA-2766 by using string ref arg and boolean return … #322

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May 15, 2024
Merged

clean-up fix for EDA-2766 by using string ref arg and boolean return … #322

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165 changes: 75 additions & 90 deletions src/synth_rapidsilicon.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -3100,30 +3100,25 @@ static void show_sig(const RTLIL::SigSpec &sig)
json_file << "\"";
}

std::string* sigName(const RTLIL::SigSpec &sig)
bool sigName(const RTLIL::SigSpec &sig, std::string& name)
{
if (!sig.is_chunk()) {
return NULL;
return false;
}

const RTLIL::SigChunk chunk = sig.as_chunk();

if (chunk.wire == NULL) {
return NULL;
return false;
}

const char* name = "\\";

if (chunk.width == chunk.wire->width && chunk.offset == 0) {
name = id(chunk.wire->name).c_str();
name = (chunk.wire->name).substr(1);
} else {
name = "";
}
// any name is prefixed with '\' so we need to remove it
name++;

std::string* sName = new std::string;
*sName = strdup(name);

return sName;
return true;
}

int checkCell(Cell* cell, const string cellName,
Expand All @@ -3134,25 +3129,25 @@ static void show_sig(const RTLIL::SigSpec &sig)
return 0;
}

std::string name;

for (auto &conn : cell->connections()) {

IdString portName = conn.first;
RTLIL::SigSpec actual = conn.second;

if (portName == RTLIL::escape_id(port1)) {
std::string* actualName = sigName(actual);
if (actualName) {
pp_group1.insert(*actualName);
pp_activeValue1.insert(*actualName);
if (sigName(actual, name)) {
pp_group1.insert(name);
pp_activeValue1.insert(name);
}
continue;
}

if (portName == RTLIL::escape_id(port2)) {
std::string* actualName = sigName(actual);
if (actualName) {
pp_group2.insert(*actualName);
pp_activeValue2.insert(*actualName);
if (sigName(actual, name)) {
pp_group2.insert(name);
pp_activeValue2.insert(name);
}
continue;
}
Expand Down Expand Up @@ -3211,9 +3206,8 @@ static void show_sig(const RTLIL::SigSpec &sig)

dumpSig(json_file, io);

std::string* ioName = sigName(io);

if (!ioName) {
std::string ioName;
if (!sigName(io, ioName)) {
continue;
}

Expand All @@ -3225,49 +3219,49 @@ static void show_sig(const RTLIL::SigSpec &sig)
json_file << " \"direction\": \"output\"";
}

if (pp_clocks.count(*ioName)) {
if (pp_clocks.count(ioName)) {
json_file << ",\n \"clock\": ";

if (pp_activeHigh.count(*ioName)) {
if (pp_activeHigh.count(ioName)) {
json_file << "\"active_high\"\n";
}
else if (pp_activeLow.count(*ioName)) {
else if (pp_activeLow.count(ioName)) {
json_file << "\"active_low\"\n";
}
}
else if (pp_asyncReset.count(*ioName)) {
else if (pp_asyncReset.count(ioName)) {
json_file << ",\n \"async_reset\": ";
if (pp_activeHigh.count(*ioName)) {
if (pp_activeHigh.count(ioName)) {
json_file << "\"active_high\"\n";
}
else if (pp_activeLow.count(*ioName)) {
else if (pp_activeLow.count(ioName)) {
json_file << "\"active_low\"\n";
}
}
else if (pp_asyncSet.count(*ioName)) {
else if (pp_asyncSet.count(ioName)) {
json_file << ",\n \"async_set\": ";
if (pp_activeHigh.count(*ioName)) {
if (pp_activeHigh.count(ioName)) {
json_file << "\"active_high\"\n";
}
else if (pp_activeLow.count(*ioName)) {
else if (pp_activeLow.count(ioName)) {
json_file << "\"active_low\"\n";
}
}
else if (pp_syncReset.count(*ioName)) {
else if (pp_syncReset.count(ioName)) {
json_file << ",\n \"sync_reset\": ";
if (pp_activeHigh.count(*ioName)) {
if (pp_activeHigh.count(ioName)) {
json_file << "\"active_high\"\n";
}
else if (pp_activeLow.count(*ioName)) {
else if (pp_activeLow.count(ioName)) {
json_file << "\"active_low\"\n";
}
}
else if (pp_syncSet.count(*ioName)) {
else if (pp_syncSet.count(ioName)) {
json_file << ",\n \"sync_set\": ";
if (pp_activeHigh.count(*ioName)) {
if (pp_activeHigh.count(ioName)) {
json_file << "\"active_high\"\n";
}
else if (pp_activeLow.count(*ioName)) {
else if (pp_activeLow.count(ioName)) {
json_file << "\"active_low\"\n";
}
}
Expand Down Expand Up @@ -3368,6 +3362,8 @@ static void show_sig(const RTLIL::SigSpec &sig)

run("splitnets -ports");

std::string name;

// visit all the cells of the design an store info.
//

Expand All @@ -3389,22 +3385,20 @@ static void show_sig(const RTLIL::SigSpec &sig)

RTLIL::SigSpec clk = cell->getPort(ID::CLK);

std::string* clkName = sigName(clk);

if (!clkName) {
if (!sigName(clk, name)) {
continue;
}

// Clock
//
pp_clocks.insert(*clkName);
pp_clocks.insert(name);

bool clk_neg_edge = RTLIL::const_eq(clk_pol, RTLIL::Const(0), false, false, 1).as_bool();

if (clk_neg_edge) {
pp_activeLow.insert(*clkName);
pp_activeLow.insert(name);
} else {
pp_activeHigh.insert(*clkName);
pp_activeHigh.insert(name);
}

continue;
Expand All @@ -3421,44 +3415,44 @@ static void show_sig(const RTLIL::SigSpec &sig)
RTLIL::Const srst_val = cell->getParam(RTLIL::escape_id("SRST_VALUE"));

RTLIL::SigSpec clk = cell->getPort(ID::CLK);
std::string* clkName = sigName(clk);
std::string clkName;

if (!clkName) {
if (!sigName(clk, clkName)) {
continue;
}

RTLIL::SigSpec srst = cell->getPort(ID::SRST);
std::string* srstName = sigName(srst);
if (!srstName) {

if (!sigName(srst, name)) {
continue;
}

// Clock
//
pp_clocks.insert(*clkName);
pp_clocks.insert(clkName);

bool clk_neg_edge = RTLIL::const_eq(clk_pol, RTLIL::Const(0), false, false, 1).as_bool();

if (clk_neg_edge) {
pp_activeLow.insert(*clkName);
pp_activeLow.insert(clkName);
} else {
pp_activeHigh.insert(*clkName);
pp_activeHigh.insert(clkName);
}

bool srst_active_low = RTLIL::const_eq(srst_pol, RTLIL::Const(0), false, false, 1).as_bool();

if (srst_active_low) {
pp_activeLow.insert(*srstName);
pp_activeLow.insert(name);
} else {
pp_activeHigh.insert(*srstName);
pp_activeHigh.insert(name);
}

bool srst_is_reset = RTLIL::const_eq(srst_val, RTLIL::Const(0), false, false, 1).as_bool();

if (srst_is_reset) {
pp_syncReset.insert(*srstName);
pp_syncReset.insert(name);
} else {
pp_syncSet.insert(*srstName);
pp_syncSet.insert(name);
}

continue;
Expand All @@ -3474,43 +3468,43 @@ static void show_sig(const RTLIL::SigSpec &sig)
RTLIL::Const arst_val = cell->getParam(RTLIL::escape_id("ARST_VALUE"));

RTLIL::SigSpec clk = cell->getPort(ID::CLK);
std::string* clkName = sigName(clk);
if (!clkName) {
std::string clkName;

if (!sigName(clk, clkName)) {
continue;
}

RTLIL::SigSpec arst = cell->getPort(ID::ARST);
std::string* arstName = sigName(arst);
if (!arstName) {

if (!sigName(arst, name)) {
continue;
}

// Clock
//
pp_clocks.insert(*clkName);
pp_clocks.insert(clkName);

bool clk_neg_edge = RTLIL::const_eq(clk_pol, RTLIL::Const(0), false, false, 1).as_bool();

if (clk_neg_edge) {
pp_activeLow.insert(*clkName);
pp_activeLow.insert(clkName);
} else {
pp_activeHigh.insert(*clkName);
pp_activeHigh.insert(clkName);
}

bool arst_active_low = RTLIL::const_eq(arst_pol, RTLIL::Const(0), false, false, 1).as_bool();

if (arst_active_low) {
pp_activeLow.insert(*arstName);
pp_activeLow.insert(name);
} else {
pp_activeHigh.insert(*arstName);
pp_activeHigh.insert(name);
}

bool arst_is_reset = RTLIL::const_eq(arst_val, RTLIL::Const(0), false, false, 1).as_bool();

if (arst_is_reset) {
pp_asyncReset.insert(*arstName);
pp_asyncReset.insert(name);
} else {
pp_asyncSet.insert(*arstName);
pp_asyncSet.insert(name);
}

continue;
Expand Down Expand Up @@ -3856,17 +3850,14 @@ static void show_sig(const RTLIL::SigSpec &sig)

RTLIL::SigSpec actual = conn.second;

std::string* actualName = sigName(actual);

if (!actualName) {
if (!sigName(actual, name)) {
continue;
}

if ((portName == RTLIL::escape_id("CLK_A")) ||
(portName == RTLIL::escape_id("CLK_B"))) {

pp_clocks.insert(*actualName);
pp_activeHigh.insert(*actualName);
pp_clocks.insert(name);
pp_activeHigh.insert(name);
continue;
}
}
Expand All @@ -3882,9 +3873,7 @@ static void show_sig(const RTLIL::SigSpec &sig)

RTLIL::SigSpec actual = conn.second;

std::string* actualName = sigName(actual);

if (!actualName) {
if (!sigName(actual, name)) {
continue;
}

Expand All @@ -3893,8 +3882,8 @@ static void show_sig(const RTLIL::SigSpec &sig)
(portName == RTLIL::escape_id("CLK_B1")) ||
(portName == RTLIL::escape_id("CLK_B2"))) {

pp_clocks.insert(*actualName);
pp_activeHigh.insert(*actualName);
pp_clocks.insert(name);
pp_activeHigh.insert(name);
continue;
}
}
Expand All @@ -3910,9 +3899,7 @@ static void show_sig(const RTLIL::SigSpec &sig)

RTLIL::SigSpec actual = conn.second;

std::string* actualName = sigName(actual);

if (!actualName) {
if (!sigName(actual, name)) {
continue;
}

Expand All @@ -3921,8 +3908,8 @@ static void show_sig(const RTLIL::SigSpec &sig)
(portName == RTLIL::escape_id("CLK_B1")) ||
(portName == RTLIL::escape_id("CLK_B2"))) {

pp_clocks.insert(*actualName);
pp_activeHigh.insert(*actualName);
pp_clocks.insert(name);
pp_activeHigh.insert(name);
continue;
}
}
Expand All @@ -3937,24 +3924,22 @@ static void show_sig(const RTLIL::SigSpec &sig)

RTLIL::SigSpec actual = conn.second;

std::string* actualName = sigName(actual);

if (!actualName) {
if (!sigName(actual, name)) {
continue;
}

if ((portName == RTLIL::escape_id("WR_CLK")) ||
(portName == RTLIL::escape_id("RD_CLK"))) {

pp_clocks.insert(*actualName);
pp_activeHigh.insert(*actualName);
pp_clocks.insert(name);
pp_activeHigh.insert(name);
continue;
}

if (portName == RTLIL::escape_id("RESET")) {

pp_syncReset.insert(*actualName);
pp_activeHigh.insert(*actualName);
pp_syncReset.insert(name);
pp_activeHigh.insert(name);
continue;
}
}
Expand Down
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