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Modifed read and wr stages to use vfpr #8

Modifed read and wr stages to use vfpr

Modifed read and wr stages to use vfpr #8

Triggered via push March 2, 2024 01:16
Status Failure
Total duration 6h 0m 15s
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Simulate SW on Snitch Cluster w/ Verilator
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Simulate SW on Snitch Cluster w/ Verilator
Simulate FDIV SW on Snitch Cluster w/ Verilator
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Simulate FDIV SW on Snitch Cluster w/ Verilator
Simulate SW on Snitch Cluster w/ Banshee
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Simulate SW on Snitch Cluster w/ Banshee
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4 errors and 64 warnings
Simulate SW on Snitch Cluster w/ Verilator
The job running on runner GitHub Actions 9 has exceeded the maximum execution time of 360 minutes.
Simulate SW on Snitch Cluster w/ Verilator
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Simulate FDIV SW on Snitch Cluster w/ Verilator
The job running on runner GitHub Actions 11 has exceeded the maximum execution time of 360 minutes.
Simulate FDIV SW on Snitch Cluster w/ Verilator
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[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L97: hw/snitch_cluster/src/snitch_fp_ss.sv#L97
Explicitly define a storage type for every parameter and localparam, (ScoreboardDepth). [Style: constants] [explicit-parameter-storage-type]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L166: hw/snitch_cluster/src/snitch_fp_ss.sv#L166
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L207: hw/snitch_cluster/src/snitch_fp_ss.sv#L207
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L312: hw/snitch_cluster/src/snitch_fp_ss.sv#L312
Line length exceeds max: 100; is: 130 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L399: hw/snitch_cluster/src/snitch_fp_ss.sv#L399
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L400: hw/snitch_cluster/src/snitch_fp_ss.sv#L400
Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L1221: hw/snitch_cluster/src/snitch_fp_ss.sv#L1221
Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L1234: hw/snitch_cluster/src/snitch_fp_ss.sv#L1234
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L1741: hw/snitch_cluster/src/snitch_fp_ss.sv#L1741
Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L1754: hw/snitch_cluster/src/snitch_fp_ss.sv#L1754
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L1799: hw/snitch_cluster/src/snitch_fp_ss.sv#L1799
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L1932: hw/snitch_cluster/src/snitch_fp_ss.sv#L1932
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L1981: hw/snitch_cluster/src/snitch_fp_ss.sv#L1981
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2190: hw/snitch_cluster/src/snitch_fp_ss.sv#L2190
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2374: hw/snitch_cluster/src/snitch_fp_ss.sv#L2374
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2383: hw/snitch_cluster/src/snitch_fp_ss.sv#L2383
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2407: hw/snitch_cluster/src/snitch_fp_ss.sv#L2407
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2455: hw/snitch_cluster/src/snitch_fp_ss.sv#L2455
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2557: hw/snitch_cluster/src/snitch_fp_ss.sv#L2557
Line length exceeds max: 100; is: 119 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2558: hw/snitch_cluster/src/snitch_fp_ss.sv#L2558
Line length exceeds max: 100; is: 119 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2559: hw/snitch_cluster/src/snitch_fp_ss.sv#L2559
Line length exceeds max: 100; is: 117 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2560: hw/snitch_cluster/src/snitch_fp_ss.sv#L2560
Line length exceeds max: 100; is: 117 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2590: hw/snitch_cluster/src/snitch_fp_ss.sv#L2590
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2787: hw/snitch_cluster/src/snitch_fp_ss.sv#L2787
Do not use consecutive null statements like ';;'. [Style: redundant-semicolons] [forbid-consecutive-null-statements]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2791: hw/snitch_cluster/src/snitch_fp_ss.sv#L2791
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2794: hw/snitch_cluster/src/snitch_fp_ss.sv#L2794
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2800: hw/snitch_cluster/src/snitch_fp_ss.sv#L2800
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2852: hw/snitch_cluster/src/snitch_fp_ss.sv#L2852
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2852: hw/snitch_cluster/src/snitch_fp_ss.sv#L2852
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/stream_stall.sv#L16: hw/snitch_cluster/src/stream_stall.sv#L16
File must end with a newline. [Style: posix-file-endings] [posix-eof]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L743: hw/snitch_cluster/src/snitch_cluster.sv#L743
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L798: hw/snitch_cluster/src/snitch_cluster.sv#L798
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L816: hw/snitch_cluster/src/snitch_cluster.sv#L816
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L861: hw/snitch_cluster/src/snitch_cluster.sv#L861
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L869: hw/snitch_cluster/src/snitch_cluster.sv#L869
Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L997: hw/snitch_cluster/src/snitch_cluster.sv#L997
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cc.sv#L972: hw/snitch_cluster/src/snitch_cc.sv#L972
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch/src/snitch_pkg.sv#L324: hw/snitch/src/snitch_pkg.sv#L324
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch/src/snitch_pkg.sv#L325: hw/snitch/src/snitch_pkg.sv#L325
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch/src/snitch_pkg.sv#L389: hw/snitch/src/snitch_pkg.sv#L389
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_router.sv#L121: hw/snitch_cluster/src/snitch_tcdm_router.sv#L121
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_router.sv#L153: hw/snitch_cluster/src/snitch_tcdm_router.sv#L153
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_vfpr.sv#L65: hw/snitch_cluster/src/snitch_vfpr.sv#L65
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_vfpr.sv#L68: hw/snitch_cluster/src/snitch_vfpr.sv#L68
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_vfpr.sv#L165: hw/snitch_cluster/src/snitch_vfpr.sv#L165
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_vfpr.sv#L221: hw/snitch_cluster/src/snitch_vfpr.sv#L221
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_vfpr.sv#L233: hw/snitch_cluster/src/snitch_vfpr.sv#L233
File must end with a newline. [Style: posix-file-endings] [posix-eof]
[verible-verilog-lint] hw/snitch_cluster/src/stream_merge.sv#L23: hw/snitch_cluster/src/stream_merge.sv#L23
File must end with a newline. [Style: posix-file-endings] [posix-eof]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L4: hw/snitch_cluster/src/snitch_sb_ipool.sv#L4
Explicitly define a storage type for every parameter and localparam, (ResetState). [Style: constants] [explicit-parameter-storage-type]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L4: hw/snitch_cluster/src/snitch_sb_ipool.sv#L4
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L102: hw/snitch_cluster/src/snitch_sb_ipool.sv#L102
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L113: hw/snitch_cluster/src/snitch_sb_ipool.sv#L113
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L122: hw/snitch_cluster/src/snitch_sb_ipool.sv#L122
File must end with a newline. [Style: posix-file-endings] [posix-eof]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L61: hw/snitch_cluster/src/snitch_sb.sv#L61
Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L69: hw/snitch_cluster/src/snitch_sb.sv#L69
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L70: hw/snitch_cluster/src/snitch_sb.sv#L70
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L76: hw/snitch_cluster/src/snitch_sb.sv#L76
All generate block statements must have a label [Style: generate-statements] [generate-label]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L91: hw/snitch_cluster/src/snitch_sb.sv#L91
File must end with a newline. [Style: posix-file-endings] [posix-eof]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_interconnect.sv#L113: hw/snitch_cluster/src/snitch_tcdm_interconnect.sv#L113
Line length exceeds max: 100; is: 217 [Style: line-length] [line-length]
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_interconnect.sv#L292: hw/snitch_cluster/src/snitch_tcdm_interconnect.sv#L292
Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
Build documentation
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v2. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
Build documentation
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/checkout@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
Simulate SW on Snitch Cluster w/ Banshee
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v2. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
Simulate SW on Snitch Cluster w/ Banshee
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/checkout@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/