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ise_hammer: 7v HR IOB.
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@wanda-phi
wanda-phi committed Oct 8, 2024
1 parent d091159 commit 119575d
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Showing 9 changed files with 1,649 additions and 296 deletions.
2 changes: 1 addition & 1 deletion databases/xc7v-tiledb.json
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8 changes: 6 additions & 2 deletions docs/gen_xilinx.py
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Original file line number Diff line number Diff line change
Expand Up @@ -377,7 +377,6 @@ def emit_dev_table_string(f, name):
emit_dev_table_bitvec(f, "MMCM:IN_DLY_SET")

if kind == "xc7v":
emit_misc_table("xilinx/gen/xc7v-hp-iostd-misc.html", "HP_IOSTD:OUTPUT_MISC")
emit_misc_table("xilinx/gen/xc7v-hp-iostd-drive.html", "HP_IOSTD:PDRIVE", "HP_IOSTD:NDRIVE")
emit_misc_table("xilinx/gen/xc7v-hp-iostd-slew.html", "HP_IOSTD:PSLEW", "HP_IOSTD:NSLEW")
emit_misc_table("xilinx/gen/xc7v-hp-iostd-lvds.html", "HP_IOSTD:LVDS_T", "HP_IOSTD:LVDS_C")
Expand All @@ -386,7 +385,12 @@ def emit_dev_table_string(f, name):
emit_misc_table("xilinx/gen/xc7v-hp-iostd-dci-output-half.html", "HP_IOSTD:DCI:PREF_OUTPUT_HALF", "HP_IOSTD:DCI:NREF_OUTPUT_HALF")
emit_misc_table("xilinx/gen/xc7v-hp-iostd-dci-term-split.html", "HP_IOSTD:DCI:NREF_TERM_SPLIT")

# TODO: HR IO
emit_misc_table("xilinx/gen/xc7v-hr-iostd-drive.html", "HR_IOSTD:DRIVE")
emit_misc_table("xilinx/gen/xc7v-hr-iostd-slew.html", "HR_IOSTD:SLEW")
emit_misc_table("xilinx/gen/xc7v-hr-iostd-misc.html", "HR_IOSTD:OUTPUT_MISC")
emit_misc_table("xilinx/gen/xc7v-hr-iostd-lvds.html", "HR_IOSTD:LVDS_T", "HR_IOSTD:LVDS_C")
emit_misc_table("xilinx/gen/xc7v-hr-iostd-driverbias.html", "HR_IOSTD:DRIVERBIAS")
emit_misc_table("xilinx/gen/xc7v-hr-iostd-lvdsbias.html", "HR_IOSTD:LVDSBIAS:COMMON", "HR_IOSTD:LVDSBIAS:GROUP")

emit_misc_table("xilinx/gen/xc7v-mmcm-filter.html", "MMCM:CP", "MMCM:RES", "MMCM:LFHF")
emit_misc_table("xilinx/gen/xc7v-mmcm-lock.html",
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24 changes: 23 additions & 1 deletion docs/xilinx/virtex7/io.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ Virtex 7 devices have a regular I/O bank structure. There are up to two I/O col
There are two genders of I/O banks:

- HP (high performance) banks, with 1.8V maximum voltage and DCI support
- HR (high range) banks, with 3.3V maxumum voltage and no DCI
- HR (high range) banks, with 3.3V maximum voltage and no DCI

In both cases, banks are 50 rows high. They have the following structure:

Expand Down Expand Up @@ -259,3 +259,25 @@ Tables — HP IO

.. raw:: html
:file: ../gen/xc7v-hp-iostd-dci-term-split.html


Tables — HR IO
==============

.. raw:: html
:file: ../gen/xc7v-hr-iostd-drive.html

.. raw:: html
:file: ../gen/xc7v-hr-iostd-slew.html

.. raw:: html
:file: ../gen/xc7v-hr-iostd-misc.html

.. raw:: html
:file: ../gen/xc7v-hr-iostd-lvds.html

.. raw:: html
:file: ../gen/xc7v-hr-iostd-driverbias.html

.. raw:: html
:file: ../gen/xc7v-hr-iostd-lvdsbias.html
10 changes: 10 additions & 0 deletions prjcombine_ise_hammer/src/backend.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@ pub enum Key<'a> {
AltVr,
InternalVref(u32),
DciCascade(u32),
VccoSenseMode(u32),
GlobalMutex(String),
RowMutex(String, RowId),
BelMutex((DieId, ColId, RowId, LayerId, BelId), String),
Expand Down Expand Up @@ -735,6 +736,7 @@ impl<'a> Backend for IseBackend<'a> {
let altvr = kv.get(&Key::AltVr) == Some(&Value::Bool(true));
let mut internal_vref = HashMap::new();
let mut dci_cascade = HashMap::new();
let mut vccosensemode = HashMap::new();
for (k, v) in &kv {
match k {
Key::DciCascade(bank) => match v {
Expand All @@ -751,13 +753,21 @@ impl<'a> Backend for IseBackend<'a> {
Value::None => (),
_ => unreachable!(),
},
Key::VccoSenseMode(bank) => match v {
Value::String(val) => {
vccosensemode.insert(*bank, val.clone());
}
Value::None => (),
_ => unreachable!(),
},
_ => (),
}
}
let pcf = Pcf {
vccaux,
internal_vref,
dci_cascade,
vccosensemode,
};
let mut key = KeyData::None;
if let Some(encrypt) = gopts.get("ENCRYPT") {
Expand Down
63 changes: 52 additions & 11 deletions prjcombine_ise_hammer/src/fgen.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -745,6 +745,7 @@ pub enum TileKV<'a> {
CenterDci(u32),
CascadeDci(u32, u32),
TouchHout(usize),
PinPair(BelId, String, BelId, String),
}

#[derive(Debug, Clone)]
Expand Down Expand Up @@ -2192,14 +2193,16 @@ impl<'a> TileKV<'a> {
col,
row: hclk_a - 24,
iob: EntityId::from_idx(0),
}].bank;
}]
.bank;
let actual_bank_b = edev.io_by_crd
[&prjcombine_virtex4::expanded::IoCoord {
die: loc.0,
col,
row: hclk_b - 24,
iob: EntityId::from_idx(0),
}].bank;
}]
.bank;
fuzzer = fuzzer.fuzz(Key::DciCascade(actual_bank_b), None, actual_bank_a);
}
_ => unreachable!(),
Expand Down Expand Up @@ -2287,6 +2290,14 @@ impl<'a> TileKV<'a> {
}
fuzzer
}
TileKV::PinPair(bel_a, pin_a, bel_b, pin_b) => {
let site_a = &backend.egrid.node(loc).bels[*bel_a];
let site_b = &backend.egrid.node(loc).bels[*bel_b];
fuzzer.base(
Key::SitePin(site_a, pin_a.clone()),
Value::FromPin(site_b, pin_b.clone()),
)
}
})
}
}
Expand Down Expand Up @@ -2589,10 +2600,10 @@ impl<'a> BelKV {
col: loc.1,
row: loc.2,
iob: prjcombine_virtex4::expanded::TileIobId::from_idx(
if edev.egrid.db.nodes.key(node.kind).starts_with("IOS") {
0
} else {
if edev.egrid.db.nodes.key(node.kind).ends_with("PAIR") {
bel.to_idx() % 2
} else {
0
},
),
}];
Expand Down Expand Up @@ -2670,10 +2681,10 @@ impl<'a> BelKV {
col: loc.1,
row: loc.2,
iob: prjcombine_virtex4::expanded::TileIobId::from_idx(
if edev.egrid.db.nodes.key(node.kind).starts_with("IOS") {
0
} else {
if edev.egrid.db.nodes.key(node.kind).ends_with("PAIR") {
bel.to_idx() % 2
} else {
0
},
),
}];
Expand Down Expand Up @@ -2834,10 +2845,10 @@ impl<'a> BelKV {
col: loc.1,
row: loc.2,
iob: prjcombine_virtex4::expanded::TileIobId::from_idx(
if edev.egrid.db.nodes.key(node.kind).starts_with("IOS") {
0
} else {
if edev.egrid.db.nodes.key(node.kind).ends_with("PAIR") {
bel.to_idx() % 2
} else {
0
},
),
}];
Expand Down Expand Up @@ -3537,6 +3548,7 @@ pub enum TileFuzzKV<'a> {
RowMutexExclusive(String),
TileRelated(TileRelation, Box<TileFuzzKV<'a>>),
PinPair(BelId, String, BelId, String),
VccoSenseMode(String),
Raw(Key<'a>, Value<'a>, Value<'a>),
}

Expand Down Expand Up @@ -3659,6 +3671,19 @@ impl<'a> TileFuzzKV<'a> {
Value::FromPin(site_b, pin_b.clone()),
)
}
TileFuzzKV::VccoSenseMode(mode) => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
unreachable!()
};
let bank = edev.io_by_crd[&prjcombine_virtex4::expanded::IoCoord {
die: loc.0,
col: loc.1,
row: loc.2,
iob: EntityId::from_idx(0),
}]
.bank;
fuzzer.fuzz(Key::VccoSenseMode(bank), None, mode.clone())
}
TileFuzzKV::Raw(ref key, ref vala, ref valb) => {
fuzzer.fuzz(key.clone(), vala.clone(), valb.clone())
}
Expand Down Expand Up @@ -4525,6 +4550,7 @@ pub enum ExtraFeatureKind {
AllXadc,
HclkIoiInnerSide(Dir),
HclkIoiHere(NodeKindId),
AllBankIo,
}

impl ExtraFeatureKind {
Expand Down Expand Up @@ -5585,6 +5611,21 @@ impl ExtraFeatureKind {
vec![]
}
}
ExtraFeatureKind::AllBankIo => {
let ExpandedDevice::Virtex4(edev) = backend.edev else {
unreachable!()
};
assert_eq!(edev.kind, prjcombine_virtex4::grid::GridKind::Virtex7);
(0..24)
.map(|i| {
let row = edev.grids[loc.0].row_hclk(loc.2) - 24 + i * 2;
vec![
edev.btile_main(loc.0, loc.1, row),
edev.btile_main(loc.0, loc.1, row + 1),
]
})
.collect()
}
}
}
}
Expand Down
3 changes: 3 additions & 0 deletions prjcombine_ise_hammer/src/fuzz.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -241,6 +241,9 @@ macro_rules! fuzz_base {
($ctx:ident, (bel_pin $bel:expr, $pin:expr)) => {
$crate::fgen::TileKV::Bel($bel, $crate::fgen::BelKV::Pin($pin.to_string(), true))
};
($ctx:ident, (pin_pair $pina:expr, $bel:expr, $pinb:expr)) => {
$crate::fgen::TileKV::PinPair($ctx.bel, $pina.to_string(), $bel, $pinb.to_string())
};
($ctx:ident, (bel_special $special:expr)) => {
$crate::fgen::TileKV::Bel($ctx.bel, $special)
};
Expand Down
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