ise_hammer: 7v HP IOB.

prjunnamed · Oct 6, 2024 · d091159 · d091159
1 parent 9a4353e
commit d091159
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Showing 18 changed files with 2,236 additions and 75 deletions.
diff --git a/databases/xc7v-tiledb.json b/databases/xc7v-tiledb.json
diff --git a/docs/gen_xilinx.py b/docs/gen_xilinx.py
@@ -377,7 +377,16 @@ def emit_dev_table_string(f, name):
             emit_dev_table_bitvec(f, "MMCM:IN_DLY_SET")
 
     if kind == "xc7v":
-        # TODO: IO
+        emit_misc_table("xilinx/gen/xc7v-hp-iostd-misc.html", "HP_IOSTD:OUTPUT_MISC")
+        emit_misc_table("xilinx/gen/xc7v-hp-iostd-drive.html", "HP_IOSTD:PDRIVE", "HP_IOSTD:NDRIVE")
+        emit_misc_table("xilinx/gen/xc7v-hp-iostd-slew.html", "HP_IOSTD:PSLEW", "HP_IOSTD:NSLEW")
+        emit_misc_table("xilinx/gen/xc7v-hp-iostd-lvds.html", "HP_IOSTD:LVDS_T", "HP_IOSTD:LVDS_C")
+        emit_misc_table("xilinx/gen/xc7v-hp-iostd-lvdsbias.html", "HP_IOSTD:LVDSBIAS")
+        emit_misc_table("xilinx/gen/xc7v-hp-iostd-dci-output.html", "HP_IOSTD:DCI:PREF_OUTPUT", "HP_IOSTD:DCI:NREF_OUTPUT")
+        emit_misc_table("xilinx/gen/xc7v-hp-iostd-dci-output-half.html", "HP_IOSTD:DCI:PREF_OUTPUT_HALF", "HP_IOSTD:DCI:NREF_OUTPUT_HALF")
+        emit_misc_table("xilinx/gen/xc7v-hp-iostd-dci-term-split.html", "HP_IOSTD:DCI:NREF_TERM_SPLIT")
+
+        # TODO: HR IO
 
         emit_misc_table("xilinx/gen/xc7v-mmcm-filter.html", "MMCM:CP", "MMCM:RES", "MMCM:LFHF")
         emit_misc_table("xilinx/gen/xc7v-mmcm-lock.html",

diff --git a/docs/xilinx/virtex7/io.rst b/docs/xilinx/virtex7/io.rst
@@ -234,3 +234,28 @@ Bitstream — ``HCLK_IOI_HR``
 
 .. raw:: html
    :file: ../gen/tile-xc7v-HCLK_IOI_HR.html
+
+
+Tables — HP IO
+==============
+
+.. raw:: html
+   :file: ../gen/xc7v-hp-iostd-drive.html
+
+.. raw:: html
+   :file: ../gen/xc7v-hp-iostd-slew.html
+
+.. raw:: html
+   :file: ../gen/xc7v-hp-iostd-lvds.html
+
+.. raw:: html
+   :file: ../gen/xc7v-hp-iostd-lvdsbias.html
+
+.. raw:: html
+   :file: ../gen/xc7v-hp-iostd-dci-output.html
+
+.. raw:: html
+   :file: ../gen/xc7v-hp-iostd-dci-output-half.html
+
+.. raw:: html
+   :file: ../gen/xc7v-hp-iostd-dci-term-split.html
diff --git a/prjcombine_hammer/src/run.rs b/prjcombine_hammer/src/run.rs
@@ -308,10 +308,7 @@ fn diagnose_cw_fail<B: Backend>(
                     fd = fuzzers[fid]
                 );
             } else {
-                eprintln!(
-                    "FUZZER {f:?}: ???",
-                    f = batch.fuzzers[fid].info,
-                );
+                eprintln!("FUZZER {f:?}: ???", f = batch.fuzzers[fid].info,);
             }
             for (k, v) in batch.fuzzers[fid].kv.iter().sorted_by_key(|x| x.0) {
                 match v {

diff --git a/prjcombine_ise_hammer/src/backend.rs b/prjcombine_ise_hammer/src/backend.rs
@@ -472,7 +472,7 @@ impl<'a> Backend for IseBackend<'a> {
         }
 
         let (dummy_inst_kind, dummy_inst_port) = match self.edev {
-            ExpandedDevice::Xc4k(_) => todo!(),
+            ExpandedDevice::Xc4k(_) => ("CLB", "K"),
             ExpandedDevice::Xc5200(_) => ("LC5A", "CK"),
             ExpandedDevice::Virtex(_) => ("SLICE", "CLK"),
             ExpandedDevice::Virtex2(edev) => (

diff --git a/prjcombine_ise_hammer/src/fgen.rs b/prjcombine_ise_hammer/src/fgen.rs
diff --git a/prjcombine_ise_hammer/src/gt/virtex7.rs b/prjcombine_ise_hammer/src/gt/virtex7.rs
@@ -1971,26 +1971,38 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         ctx.collect_enum_default(tile, bel, "QPLLREFCLKSEL_MODE", &["DYNAMIC"], "STATIC");
         let node = ctx.edev.egrid().db.get_node(tile);
         if ctx.edev.egrid().node_index[node].len() > 1 {
-            ctx.collect_enum_default_ocd(tile, bel, "MUX.NORTHREFCLK0_N", &[
-                "REFCLK0",
-                "REFCLK1",
-                "NORTHREFCLK0",
-            ], "NONE", OcdMode::BitOrderDrpV6);
-            ctx.collect_enum_default_ocd(tile, bel, "MUX.NORTHREFCLK1_N", &[
-                "REFCLK0",
-                "REFCLK1",
-                "NORTHREFCLK1",
-            ], "NONE", OcdMode::BitOrderDrpV6);
-            ctx.collect_enum_default_ocd(tile, bel, "MUX.SOUTHREFCLK0_S", &[
-                "REFCLK0",
-                "REFCLK1",
-                "SOUTHREFCLK0",
-            ], "NONE", OcdMode::BitOrderDrpV6);
-            ctx.collect_enum_default_ocd(tile, bel, "MUX.SOUTHREFCLK1_S", &[
-                "REFCLK0",
-                "REFCLK1",
-                "SOUTHREFCLK1",
-            ], "NONE", OcdMode::BitOrderDrpV6);
+            ctx.collect_enum_default_ocd(
+                tile,
+                bel,
+                "MUX.NORTHREFCLK0_N",
+                &["REFCLK0", "REFCLK1", "NORTHREFCLK0"],
+                "NONE",
+                OcdMode::BitOrderDrpV6,
+            );
+            ctx.collect_enum_default_ocd(
+                tile,
+                bel,
+                "MUX.NORTHREFCLK1_N",
+                &["REFCLK0", "REFCLK1", "NORTHREFCLK1"],
+                "NONE",
+                OcdMode::BitOrderDrpV6,
+            );
+            ctx.collect_enum_default_ocd(
+                tile,
+                bel,
+                "MUX.SOUTHREFCLK0_S",
+                &["REFCLK0", "REFCLK1", "SOUTHREFCLK0"],
+                "NONE",
+                OcdMode::BitOrderDrpV6,
+            );
+            ctx.collect_enum_default_ocd(
+                tile,
+                bel,
+                "MUX.SOUTHREFCLK1_S",
+                &["REFCLK0", "REFCLK1", "SOUTHREFCLK1"],
+                "NONE",
+                OcdMode::BitOrderDrpV6,
+            );
         }
     }
     for (tile, bel_common) in [

diff --git a/prjcombine_ise_hammer/src/io/virtex6.rs b/prjcombine_ise_hammer/src/io/virtex6.rs
@@ -1090,11 +1090,13 @@ pub fn add_fuzzers<'a>(
         }
 
         fuzz_one!(ctx, "OUTPUT_DELAY", "0", [
+            (mutex "OUTPUT_DELAY", "0"),
             (bel_mode bel_ologic, "OLOGICE1")
         ], [
             (pip (bel_pin bel_ologic, "OQ"), (bel_pin bel_ologic, "IOB_O"))
         ]);
         fuzz_one!(ctx, "OUTPUT_DELAY", "1", [
+            (mutex "OUTPUT_DELAY", "1"),
             (bel_mode bel_ologic, "OLOGICE1")
         ], [
             (pip (bel_pin bel_iodelay, "DATAOUT"), (bel_pin bel_ologic, "IOB_O"))