virtex_bitstream: ECC.

prjunnamed · Oct 16, 2024 · 2d52946 · 2d52946
1 parent 19dd549
commit 2d52946
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Showing 28 changed files with 1,106 additions and 72 deletions.
diff --git a/Cargo.toml b/Cargo.toml
@@ -123,6 +123,7 @@ indexmap = { version = "2", features = ["serde"] }
 ndarray = { version = "0.16", features = ["serde"] }
 enum-map = { version = "2.4", features = ["serde"] }
 bitvec = { version = "1.0", features = ["serde"] }
+arrayvec = { version = "0.7.6", features = ["serde"] }
 itertools = "0.13"
 rand = { version = "0.8", features = ["small_rng"] }
 nix = { version = "0.29", features = ["fs"] }

diff --git a/databases/xc6v-tiledb.json b/databases/xc6v-tiledb.json
diff --git a/databases/xc7v-tiledb.json b/databases/xc7v-tiledb.json
diff --git a/docs/xilinx/virtex7/pcie.rst b/docs/xilinx/virtex7/pcie.rst
@@ -2,15 +2,8 @@ PCI Express Gen2 cores
 ######################
 
 
-``PCIE_L``
-==========
+Bitstream
+=========
 
 .. raw:: html
-   :file: ../gen/tile-xc7v-PCIE_L.html
-
-
-``PCIE_R``
-==========
-
-.. raw:: html
-   :file: ../gen/tile-xc7v-PCIE_R.html
+   :file: ../gen/tile-xc7v-PCIE.html
diff --git a/prjcombine_ise_hammer/src/fgen.rs b/prjcombine_ise_hammer/src/fgen.rs
@@ -4421,9 +4421,6 @@ impl TileBits {
                     unreachable!()
                 };
                 let mut res = vec![];
-                for i in 0..50 {
-                    res.push(edev.btile_main(die, col, row + i));
-                }
                 for i in 0..50 {
                     res.push(edev.btile_main(die, col + 4, row + i));
                 }
@@ -5100,7 +5097,11 @@ impl ExtraFeatureKind {
                 let ExpandedDevice::Virtex4(edev) = backend.edev else {
                     unreachable!()
                 };
-                let col = loc.1 - 1;
+                let col = if loc.1.to_idx() % 2 == 0 {
+                    loc.1 - 4
+                } else {
+                    loc.1 - 1
+                };
                 let row = loc.2 + edev.grids[loc.0].rows_per_reg() / 2;
                 vec![vec![
                     edev.btile_hclk(loc.0, col, row),

diff --git a/prjcombine_ise_hammer/src/io/virtex6.rs b/prjcombine_ise_hammer/src/io/virtex6.rs
@@ -443,10 +443,12 @@ pub fn add_fuzzers<'a>(
 
         fuzz_enum!(ctx, "OUTFFTYPE", ["#FF", "#LATCH", "DDR"], [
             (mode "OLOGICE1"),
+            (attr "TFFTYPE", ""),
             (pin "OQ")
         ]);
         fuzz_enum!(ctx, "TFFTYPE", ["#FF", "#LATCH", "DDR"], [
             (mode "OLOGICE1"),
+            (attr "OUTFFTYPE", ""),
             (pin "TQ")
         ]);
 

diff --git a/prjcombine_ise_hammer/src/pcie/virtex6.rs b/prjcombine_ise_hammer/src/pcie/virtex6.rs
@@ -1,7 +1,8 @@
 use prjcombine_hammer::Session;
+use prjcombine_types::TileItem;
 
 use crate::{
-    backend::IseBackend,
+    backend::{FeatureBit, IseBackend},
     diff::CollectorCtx,
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
@@ -284,6 +285,22 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     }
     let tile = "PCIE";
     let bel = "PCIE";
+
+    fn pcie_drp_bit(reg: usize, bit: usize) -> FeatureBit {
+        let tile = reg / 6;
+        let frame = 26 + (bit & 1);
+        let bit = (bit >> 1) | (reg % 6) << 3;
+        FeatureBit::new(tile, frame, bit)
+    }
+    for reg in 0..0x78 {
+        ctx.tiledb.insert(
+            tile,
+            bel,
+            format!("DRP{reg:02X}"),
+            TileItem::from_bitvec((0..16).map(|bit| pcie_drp_bit(reg, bit)).collect(), false),
+        );
+    }
+
     ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
     for &attr in PCIE_BOOL_ATTRS {
         ctx.collect_enum_bool(tile, bel, attr, "FALSE", "TRUE");

diff --git a/prjcombine_ise_hammer/src/pcie/virtex7.rs b/prjcombine_ise_hammer/src/pcie/virtex7.rs
@@ -1,7 +1,8 @@
 use prjcombine_hammer::Session;
+use prjcombine_types::TileItem;
 
 use crate::{
-    backend::IseBackend,
+    backend::{FeatureBit, IseBackend},
     diff::CollectorCtx,
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
@@ -631,11 +632,7 @@ const PCIE3_DEC_ATTRS: &[(&str, usize)] = &[
 ];
 
 pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBackend<'a>) {
-    for tile in ["PCIE_L", "PCIE_R"] {
-        let Some(ctx) = FuzzCtx::try_new(session, backend, tile, "PCIE", TileBits::MainAuto) else {
-            continue;
-        };
-
+    if let Some(ctx) = FuzzCtx::try_new(session, backend, "PCIE", "PCIE", TileBits::MainAuto) {
         fuzz_one!(ctx, "PRESENT", "1", [], [(mode "PCIE_2_1")]);
         // always appears in left column even when DRP is in right column — bug or intentional?
         let extras = vec![ExtraFeature::new(
@@ -683,11 +680,25 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
 
 pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     let mut got_pcie = false;
-    for tile in ["PCIE_L", "PCIE_R"] {
-        if !ctx.has_tile(tile) {
-            continue;
-        }
+    if ctx.has_tile("PCIE") {
+        let tile = "PCIE";
         let bel = "PCIE";
+
+        fn pcie_drp_bit(reg: usize, bit: usize) -> FeatureBit {
+            let tile = reg / 6;
+            let frame = 28 + (bit & 1);
+            let bit = (bit >> 1) | (reg % 6) << 3;
+            FeatureBit::new(tile, frame, bit)
+        }
+        for reg in 0..0x96 {
+            ctx.tiledb.insert(
+                tile,
+                bel,
+                format!("DRP{reg:02X}"),
+                TileItem::from_bitvec((0..16).map(|bit| pcie_drp_bit(reg, bit)).collect(), false),
+            );
+        }
+
         ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
         ctx.state
             .get_diff(tile, bel, "DRP_MASK", "1")

diff --git a/prjcombine_spartan6/src/expand.rs b/prjcombine_spartan6/src/expand.rs
@@ -2391,6 +2391,7 @@ impl Expander<'_, '_> {
                         major,
                         minor: minor as u32,
                     },
+                    mask_mode: [].into_iter().collect(),
                 });
             }
             major += 1;
@@ -2404,6 +2405,7 @@ impl Expander<'_, '_> {
                             major,
                             minor: minor as u32,
                         },
+                        mask_mode: [].into_iter().collect(),
                     });
                 }
                 major += 1;
@@ -2418,6 +2420,7 @@ impl Expander<'_, '_> {
                                 major: bram_major,
                                 minor,
                             },
+                            mask_mode: [].into_iter().collect(),
                         });
                     }
                     bram_major += 1;

diff --git a/prjcombine_virtex/src/expand.rs b/prjcombine_virtex/src/expand.rs
@@ -722,6 +722,7 @@ impl Expander<'_, '_> {
                     major,
                     minor,
                 },
+                mask_mode: [].into_iter().collect(),
             });
         }
         major += 1;
@@ -771,6 +772,7 @@ impl Expander<'_, '_> {
                             major,
                             minor,
                         },
+                        mask_mode: [].into_iter().collect(),
                     });
                 }
                 major += 1;
@@ -798,6 +800,7 @@ impl Expander<'_, '_> {
                                 major,
                                 minor,
                             },
+                            mask_mode: [].into_iter().collect(),
                         });
                     }
                     major += 1;
@@ -831,6 +834,7 @@ impl Expander<'_, '_> {
                             major,
                             minor,
                         },
+                        mask_mode: [].into_iter().collect(),
                     });
                 }
                 major += 1;

diff --git a/prjcombine_virtex2/src/expand.rs b/prjcombine_virtex2/src/expand.rs
@@ -36,7 +36,7 @@ struct Expander<'a, 'b> {
     bram_frame: EntityPartVec<ColId, usize>,
 }
 
-impl<'a, 'b> Expander<'a, 'b> {
+impl Expander<'_, '_> {
     fn is_hole(&self, col: ColId, row: RowId) -> bool {
         for hole in &self.holes {
             if hole.contains(col, row) {
@@ -3514,6 +3514,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                     major,
                     minor,
                 },
+                mask_mode: [].into_iter().collect(),
             });
         }
         major += 1;
@@ -3527,6 +3528,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                     major,
                     minor,
                 },
+                mask_mode: [].into_iter().collect(),
             });
         }
         major += 1;
@@ -3545,6 +3547,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                         major,
                         minor,
                     },
+                    mask_mode: [].into_iter().collect(),
                 });
             }
             major += 1;
@@ -3558,6 +3561,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                     major,
                     minor,
                 },
+                mask_mode: [].into_iter().collect(),
             });
         }
 
@@ -3576,6 +3580,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                         major,
                         minor,
                     },
+                    mask_mode: [].into_iter().collect(),
                 });
             }
             major += 1;
@@ -3595,6 +3600,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                         major,
                         minor,
                     },
+                    mask_mode: [].into_iter().collect(),
                 });
             }
             major += 1;

diff --git a/prjcombine_virtex4/src/expand/virtex4.rs b/prjcombine_virtex4/src/expand/virtex4.rs
@@ -1,7 +1,7 @@
 use prjcombine_int::db::IntDb;
 use prjcombine_int::grid::{ColId, DieId, ExpandedDieRefMut, ExpandedGrid, Rect, RowId};
 use prjcombine_virtex_bitstream::{
-    BitstreamGeom, DeviceKind, DieBitstreamGeom, FrameAddr, FrameInfo,
+    BitstreamGeom, DeviceKind, DieBitstreamGeom, FrameAddr, FrameInfo, FrameMaskMode,
 };
 use unnamed_entity::{EntityId, EntityPartVec, EntityVec};
 
@@ -1174,13 +1174,39 @@ impl Expander<'_, '_> {
                     continue;
                 }
                 for minor in 0..width {
+                    let mut mask_mode = [FrameMaskMode::None; 4];
+                    if cd == ColumnKind::Gt && minor == 19 {
+                        mask_mode = [FrameMaskMode::DrpV4; 4];
+                    }
+                    if cd == ColumnKind::Cfg {
+                        for &(row, kind) in &self.grid.rows_cfg {
+                            if self.grid.row_to_reg(row) == reg {
+                                let idx = row.to_idx() / 4 % 4;
+                                match kind {
+                                    CfgRowKind::Dcm => {
+                                        if matches!(minor, 19 | 20) {
+                                            mask_mode[idx] = FrameMaskMode::DrpV4;
+                                        }
+                                    }
+                                    CfgRowKind::Ccm => (),
+                                    CfgRowKind::Sysmon => {
+                                        if matches!(minor, 19 | 20 | 21 | 24 | 25 | 26 | 27 | 28) {
+                                            mask_mode[idx] = FrameMaskMode::All;
+                                            mask_mode[idx + 1] = FrameMaskMode::All;
+                                        }
+                                    }
+                                }
+                            }
+                        }
+                    }
                     self.frame_info.push(FrameInfo {
                         addr: FrameAddr {
                             typ: 0,
                             region: (reg - self.grid.reg_cfg) as i32,
                             major,
                             minor,
                         },
+                        mask_mode: mask_mode.into_iter().collect(),
                     });
                 }
                 major += 1;
@@ -1194,6 +1220,7 @@ impl Expander<'_, '_> {
                                 major,
                                 minor,
                             },
+                            mask_mode: [FrameMaskMode::None; 4].into_iter().collect(),
                         });
                     }
                     major += 1;
@@ -1208,13 +1235,19 @@ impl Expander<'_, '_> {
                 }
                 self.frames.col_frame[reg][col] = self.frame_info.len();
                 for minor in 0..20 {
+                    let mask_mode = if minor == 19 {
+                        FrameMaskMode::BramV4
+                    } else {
+                        FrameMaskMode::None
+                    };
                     self.frame_info.push(FrameInfo {
                         addr: FrameAddr {
                             typ: 1,
                             region: (reg - self.grid.reg_cfg) as i32,
                             major,
                             minor,
                         },
+                        mask_mode: [mask_mode; 4].into_iter().collect(),
                     });
                 }
                 major += 1;
@@ -1235,6 +1268,7 @@ impl Expander<'_, '_> {
                             major,
                             minor,
                         },
+                        mask_mode: [FrameMaskMode::All; 4].into_iter().collect(),
                     });
                 }
                 major += 1;