Deploying to gh-pages from @ 7d631ac 🚀

_sources/xilinx/virtex5/cmt.rst.txt

@@ -0,0 +1,23 @@
+.. _virtex5-cmt:
+
+Clock management tile
+#####################
+
+.. todo:: describe this madness
+
+
+``CMT``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc5v-CMT.html
+
+
+Tables
+======
+
+.. raw:: html
+   :file: ../gen/xc5v-pll-filter.html
+
+.. raw:: html
+   :file: ../gen/xc5v-pll-in-dly-set.html

_sources/xilinx/virtex5/index.rst.txt

@@ -15,6 +15,7 @@ Virtex 5
    io
    center
    clock
+   cmt
    ppc
    emac
    pcie

_sources/xilinx/virtex6/cmt.rst.txt

@@ -0,0 +1,26 @@
+.. _virtex6-cmt:
+
+Clock management tile
+#####################
+
+.. todo:: describe this madness
+
+
+``CMT``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-CMT.html
+
+
+Tables
+======
+
+.. raw:: html
+   :file: ../gen/xc6v-mmcm-filter.html
+
+.. raw:: html
+   :file: ../gen/xc6v-mmcm-lock.html
+
+.. raw:: html
+   :file: ../gen/xc6v-mmcm-in-dly-set.html

_sources/xilinx/virtex6/index.rst.txt

@@ -15,6 +15,7 @@ Virtex 6
    io
    center
    clock
+   cmt
    emac
    pcie
    gtx

_sources/xilinx/virtex7/center.rst.txt

@@ -0,0 +1,20 @@
+.. _virtex7-center:
+
+Configuration Center
+####################
+
+.. todo:: document
+
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CFG.html
+
+
+XADC
+====
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-XADC.html

_sources/xilinx/virtex7/cmt.rst.txt

@@ -18,3 +18,23 @@ Clock management tile
 
 .. raw:: html
    :file: ../gen/tile-xc7v-CMT_FIFO.html
+
+
+MMCM Tables
+===========
+
+.. raw:: html
+   :file: ../gen/xc7v-mmcm-filter.html
+
+.. raw:: html
+   :file: ../gen/xc7v-mmcm-lock.html
+
+
+PLL Tables
+==========
+
+.. raw:: html
+   :file: ../gen/xc7v-pll-filter.html
+
+.. raw:: html
+   :file: ../gen/xc7v-pll-lock.html

_sources/xilinx/virtex7/config.rst.txt

@@ -0,0 +1,82 @@
+.. _virtex7-config:
+
+Configuration registers
+#######################
+
+.. todo:: document
+
+``COR``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.COR.html
+
+
+``COR1``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.COR1.html
+
+
+``CTL``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.CTL.html
+
+
+``CTL1``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.CTL1.html
+
+
+``BSPI``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.BSPI.html
+
+
+``WBSTAR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.WBSTAR.html
+
+
+``TIMER``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.TIMER.html
+
+
+``TESTMODE``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.TESTMODE.html
+
+
+``TRIM0``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.TRIM0.html
+
+
+``TRIM1``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.TRIM1.html
+
+
+``TRIM2``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-REG.TRIM2.html

_sources/xilinx/virtex7/index.rst.txt

@@ -13,7 +13,9 @@ Virtex 7
    bram
    dsp
    io
+   center
    clock
    cmt
    pcie
    pcie3
+   config

_sources/xilinx/virtex7/io.rst.txt

@@ -178,3 +178,17 @@ The devices also have dedicated configuration bank 0, which has no user I/O and
 - ``M0``, ``M1``, ``M2``
 - ``PROGRAM_B``
 - ``TCK``, ``TDI``, ``TDO``, ``TMS``
+
+
+Bitstream — ``HCLK_IOI_HP``
+===========================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-HCLK_IOI_HP.html
+
+
+Bitstream — ``HCLK_IOI_HR``
+===========================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-HCLK_IOI_HR.html

xilinx/index.html

@@ -191,6 +191,7 @@ <h1>Xilinx FPGAs<a class="headerlink" href="#xilinx-fpgas" title="Link to this h
 <li class="toctree-l2"><a class="reference internal" href="virtex5/io.html">Input/Output</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex5/center.html">Configuration Center</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex5/clock.html">Clock interconnect</a></li>
+<li class="toctree-l2"><a class="reference internal" href="virtex5/cmt.html">Clock management tile</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex5/ppc.html">PowerPC cores</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex5/emac.html">Ethernet MACs</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex5/pcie.html">PCI Express cores</a></li>
@@ -208,6 +209,7 @@ <h1>Xilinx FPGAs<a class="headerlink" href="#xilinx-fpgas" title="Link to this h
 <li class="toctree-l2"><a class="reference internal" href="virtex6/io.html">Input/Output</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/center.html">Configuration Center</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/clock.html">Clock interconnect</a></li>
+<li class="toctree-l2"><a class="reference internal" href="virtex6/cmt.html">Clock management tile</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/emac.html">Ethernet MACs</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/pcie.html">PCI Express cores</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/gtx.html">GTX transceivers</a></li>
@@ -222,10 +224,12 @@ <h1>Xilinx FPGAs<a class="headerlink" href="#xilinx-fpgas" title="Link to this h
 <li class="toctree-l2"><a class="reference internal" href="virtex7/bram.html">Block RAM</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/dsp.html">DSP</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/io.html">Input/Output</a></li>
+<li class="toctree-l2"><a class="reference internal" href="virtex7/center.html">Configuration Center</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/clock.html">Clock interconnect</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/cmt.html">Clock management tile</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/pcie.html">PCI Express Gen2 cores</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/pcie3.html">PCI Express Gen3 cores</a></li>
+<li class="toctree-l2"><a class="reference internal" href="virtex7/config.html">Configuration registers</a></li>
 </ul>
 </li>
 </ul>