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_sources/xilinx/virtex7/clock.rst.txt

@@ -0,0 +1,41 @@
+.. _virtex7-clock:
+
+Clock interconnect
+##################
+
+.. todo:: describe this madness
+
+
+``HCLK``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-HCLK.html
+
+
+``CLK_BUFG``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CLK_BUFG.html
+
+
+``CLK_HROW``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CLK_HROW.html
+
+
+``CLK_BUFG_REBUF``
+==================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CLK_BUFG_REBUF.html
+
+
+``CLK_BALI_REBUF``
+==================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CLK_BALI_REBUF.html

_sources/xilinx/virtex7/cmt.rst.txt

@@ -0,0 +1,20 @@
+.. _virtex7-cmt:
+
+Clock management tile
+#####################
+
+.. todo:: describe this madness
+
+
+``CMT``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CMT.html
+
+
+``CMT_FIFO``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CMT_FIFO.html

_sources/xilinx/virtex7/index.rst.txt

@@ -13,5 +13,7 @@ Virtex 7
    bram
    dsp
    io
+   clock
+   cmt
    pcie
    pcie3

xilinx/index.html

@@ -222,6 +222,8 @@ <h1>Xilinx FPGAs<a class="headerlink" href="#xilinx-fpgas" title="Link to this h
 <li class="toctree-l2"><a class="reference internal" href="virtex7/bram.html">Block RAM</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/dsp.html">DSP</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/io.html">Input/Output</a></li>
+<li class="toctree-l2"><a class="reference internal" href="virtex7/clock.html">Clock interconnect</a></li>
+<li class="toctree-l2"><a class="reference internal" href="virtex7/cmt.html">Clock management tile</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/pcie.html">PCI Express Gen2 cores</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex7/pcie3.html">PCI Express Gen3 cores</a></li>
 </ul>

xilinx/spartan6/clock.html

@@ -5774,9 +5774,43 @@ <h2>Bitstream — <code class="docutils literal notranslate"><span class="pre">P
 <h2><code class="docutils literal notranslate"><span class="pre">PCI_CE_DELAY</span></code><a class="headerlink" href="#pci-ce-delay" title="Link to this heading"></a></h2>
 <table class="docutils align-default">
 <tr><th>Device</th><th>Value</th></tr>
+<tr><td>xa6slx100</td><td>TAP9</td</tr>
+<tr><td>xa6slx16</td><td>TAP6</td</tr>
+<tr><td>xa6slx25</td><td>TAP6</td</tr>
+<tr><td>xa6slx25t</td><td>TAP6</td</tr>
+<tr><td>xa6slx4</td><td>TAP6</td</tr>
+<tr><td>xa6slx45</td><td>TAP6</td</tr>
+<tr><td>xa6slx45t</td><td>TAP6</td</tr>
+<tr><td>xa6slx75</td><td>TAP9</td</tr>
+<tr><td>xa6slx75t</td><td>TAP9</td</tr>
+<tr><td>xa6slx9</td><td>TAP6</td</tr>
+<tr><td>xc6slx100</td><td>TAP9</td</tr>
+<tr><td>xc6slx100l</td><td>TAP9</td</tr>
+<tr><td>xc6slx100t</td><td>TAP9</td</tr>
+<tr><td>xc6slx150</td><td>TAP9</td</tr>
+<tr><td>xc6slx150l</td><td>TAP9</td</tr>
+<tr><td>xc6slx150t</td><td>TAP9</td</tr>
+<tr><td>xc6slx16</td><td>TAP6</td</tr>
+<tr><td>xc6slx16l</td><td>TAP6</td</tr>
+<tr><td>xc6slx25</td><td>TAP6</td</tr>
+<tr><td>xc6slx25l</td><td>TAP6</td</tr>
 <tr><td>xc6slx25t</td><td>TAP6</td</tr>
+<tr><td>xc6slx4</td><td>TAP6</td</tr>
+<tr><td>xc6slx45</td><td>TAP6</td</tr>
+<tr><td>xc6slx45l</td><td>TAP6</td</tr>
+<tr><td>xc6slx45t</td><td>TAP6</td</tr>
+<tr><td>xc6slx4l</td><td>TAP6</td</tr>
+<tr><td>xc6slx75</td><td>TAP9</td</tr>
+<tr><td>xc6slx75l</td><td>TAP9</td</tr>
 <tr><td>xc6slx75t</td><td>TAP9</td</tr>
 <tr><td>xc6slx9</td><td>TAP6</td</tr>
+<tr><td>xc6slx9l</td><td>TAP6</td</tr>
+<tr><td>xq6slx150</td><td>TAP9</td</tr>
+<tr><td>xq6slx150l</td><td>TAP9</td</tr>
+<tr><td>xq6slx150t</td><td>TAP9</td</tr>
+<tr><td>xq6slx75</td><td>TAP9</td</tr>
+<tr><td>xq6slx75l</td><td>TAP9</td</tr>
+<tr><td>xq6slx75t</td><td>TAP9</td</tr>
 </table>
 </section>
 </section>

xilinx/virtex5/io.html

@@ -541,9 +541,46 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <table class="docutils align-default">
 <tr><th rowspan="2">Device</th><th colspan="6">IODELAY:DEFAULT_IDELAY_VALUE</th></tr>
 <tr><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>xc5vfx100t</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>xc5vfx130t</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vfx200t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>xc5vfx30t</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vfx70t</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vlx110</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vlx110t</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vlx155</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>xc5vlx155t</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>xc5vlx20t</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vlx220</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vlx220t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vlx30</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vlx30t</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vlx330</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>xc5vlx330t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vlx50</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vlx50t</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vlx85</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vlx85t</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vsx240t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xc5vsx35t</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vsx50t</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vsx95t</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
 <tr><td>xc5vtx150t</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xc5vtx240t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vfx100t</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>xq5vfx130t</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xq5vfx200t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vfx70t</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vlx110</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vlx110t</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vlx155t</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>xq5vlx220t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vlx30t</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>xq5vlx330t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vlx85</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vsx240t</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>xq5vsx50t</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>xq5vsx95t</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
 <tr><th colspan="39">IO bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="38">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th><th>34</th><th>35</th><th>36</th><th>37</th></tr>

xilinx/virtex7/bram.html

@@ -67,6 +67,8 @@
 </li>
 <li class="toctree-l3"><a class="reference internal" href="dsp.html">DSP</a></li>
 <li class="toctree-l3"><a class="reference internal" href="io.html">Input/Output</a></li>
+<li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="cmt.html">Clock management tile</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express Gen2 cores</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie3.html">PCI Express Gen3 cores</a></li>
 </ul>

xilinx/virtex7/clb.html

@@ -68,6 +68,8 @@
 <li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM</a></li>
 <li class="toctree-l3"><a class="reference internal" href="dsp.html">DSP</a></li>
 <li class="toctree-l3"><a class="reference internal" href="io.html">Input/Output</a></li>
+<li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="cmt.html">Clock management tile</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express Gen2 cores</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie3.html">PCI Express Gen3 cores</a></li>
 </ul>