ise_hammer: 7v GTP/GTX/GTH.

prjunnamed · Oct 5, 2024 · 9a4353e · 9a4353e
1 parent fe0a267
commit 9a4353e
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diff --git a/databases/xc7v-tiledb.json b/databases/xc7v-tiledb.json
diff --git a/docs/xilinx/virtex7/gth.rst b/docs/xilinx/virtex7/gth.rst
@@ -0,0 +1,20 @@
+.. _virtex7-gth:
+
+GTH transceivers
+################
+
+.. todo:: document
+
+
+``GTH_COMMON``
+==============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-GTH_COMMON.html
+
+
+``GTH_CHANNEL``
+===============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-GTH_CHANNEL.html
diff --git a/docs/xilinx/virtex7/gtp.rst b/docs/xilinx/virtex7/gtp.rst
@@ -0,0 +1,34 @@
+.. _virtex7-gtp:
+
+GTP transceivers
+################
+
+.. todo:: document
+
+
+``GTP_COMMON``
+==============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-GTP_COMMON.html
+
+
+``GTP_CHANNEL``
+===============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-GTP_CHANNEL.html
+
+
+``GTP_COMMON_MID``
+==================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-GTP_COMMON_MID.html
+
+
+``GTP_CHANNEL_MID``
+===================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-GTP_CHANNEL_MID.html
diff --git a/docs/xilinx/virtex7/gtx.rst b/docs/xilinx/virtex7/gtx.rst
@@ -0,0 +1,20 @@
+.. _virtex7-gtx:
+
+GTX transceivers
+################
+
+.. todo:: document
+
+
+``GTX_COMMON``
+==============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-GTX_COMMON.html
+
+
+``GTX_CHANNEL``
+===============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-GTX_CHANNEL.html
diff --git a/docs/xilinx/virtex7/index.rst b/docs/xilinx/virtex7/index.rst
@@ -18,4 +18,7 @@ Virtex 7
    cmt
    pcie
    pcie3
+   gtp
+   gtx
+   gth
    config
diff --git a/prjcombine_ise_hammer/src/fgen.rs b/prjcombine_ise_hammer/src/fgen.rs
@@ -3588,6 +3588,8 @@ pub enum TileBits {
     Cmt,
     Mgt,
     DoubleHclk,
+    GtpCommonMid,
+    GtpChannelMid,
 }
 
 impl TileBits {
@@ -4176,6 +4178,38 @@ impl TileBits {
                     edev.btile_hclk(loc.0, loc.1 + 1, loc.2),
                 ]
             }
+            TileBits::GtpCommonMid => {
+                let ExpandedDevice::Virtex4(edev) = backend.edev else {
+                    unreachable!()
+                };
+                assert_eq!(edev.kind, prjcombine_virtex4::grid::GridKind::Virtex7);
+                let col = if loc.1.to_idx() % 2 == 0 {
+                    loc.1 - 1
+                } else {
+                    loc.1 + 1
+                };
+                vec![
+                    edev.btile_main(loc.0, col, loc.2 - 3),
+                    edev.btile_main(loc.0, col, loc.2 - 2),
+                    edev.btile_main(loc.0, col, loc.2 - 1),
+                    edev.btile_main(loc.0, col, loc.2),
+                    edev.btile_main(loc.0, col, loc.2 + 1),
+                    edev.btile_main(loc.0, col, loc.2 + 2),
+                    edev.btile_hclk(loc.0, col, loc.2),
+                ]
+            }
+            TileBits::GtpChannelMid => {
+                let ExpandedDevice::Virtex4(edev) = backend.edev else {
+                    unreachable!()
+                };
+                assert_eq!(edev.kind, prjcombine_virtex4::grid::GridKind::Virtex7);
+                let col = if loc.1.to_idx() % 2 == 0 {
+                    loc.1 - 1
+                } else {
+                    loc.1 + 1
+                };
+                (0..11).map(|i| edev.btile_main(loc.0, col, loc.2 + i)).collect()
+            }
         }
     }
 }

diff --git a/prjcombine_ise_hammer/src/gt.rs b/prjcombine_ise_hammer/src/gt.rs
@@ -5,3 +5,4 @@ pub mod virtex4;
 pub mod virtex5;
 pub mod virtex6_gth;
 pub mod virtex6_gtx;
+pub mod virtex7;
-Original file line number
+Diff line change
@@ Expand Up / @@ -18,4 +18,7 @@ Virtex 7 @@
        cmt
        pcie
        pcie3
+       gtp
+       gtx
+       gth
        config