ise_hammer: 7v IOI.

prjunnamed · Oct 3, 2024 · fe0a267 · fe0a267
1 parent 999dc0c
commit fe0a267
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diff --git a/databases/xc7v-tiledb.json b/databases/xc7v-tiledb.json
diff --git a/docs/xilinx/virtex7/io.rst b/docs/xilinx/virtex7/io.rst
@@ -14,9 +14,9 @@ There are two genders of I/O banks:
 
 In both cases, banks are 50 rows high. They have the following structure:
 
-- row 0: contains a ``IOS_HP`` or ``IOS_HR`` tile with a single unpaired IOB
-- rows 1-2, 3-4, 5-6, 7-8, ..., 45-46, 47-48: contain ``IOP_HP`` or ``IOP_HR`` tiles, which are two rows high and contain two IOBs each, forming a differential pair; ``IOB0`` is located in the bottom (odd) row and is the "complemented" pin of the pair, while ``IOB1`` is in the top (even) row and is the "true" pin of the pair
-- row 49: contains another ``IOS_HP`` or ``IOS_HR`` tile
+- row 0: contains a ``IO_HP_BOT`` or ``IO_HR_BOT`` tile with a single unpaired IOB
+- rows 1-2, 3-4, 5-6, 7-8, ..., 45-46, 47-48: contain ``IO_HP_PAIR`` or ``IO_HR_PAIR`` tiles, which are two rows high and contain two IOBs each, forming a differential pair; ``IOB0`` is located in the bottom (odd) row and is the "complemented" pin of the pair, while ``IOB1`` is in the top (even) row and is the "true" pin of the pair
+- row 49: contains another ``IO_HP_TOP`` or ``IO_HR_TOP`` tile
 - HCLK row: contains an ``HCLK_IO_HP`` or ``HCLK_IO_HR`` tile with common bank circuitry
 
 The single IOB in row 0 is the VRP pin for DCI. The single IOB in row 49 is VRN pin.
@@ -180,6 +180,48 @@ The devices also have dedicated configuration bank 0, which has no user I/O and
 - ``TCK``, ``TDI``, ``TDO``, ``TMS``
 
 
+Bitstream — ``IO_HP_PAIR``
+==========================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-IO_HP_PAIR.html
+
+
+Bitstream — ``IO_HP_BOT``
+=========================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-IO_HP_BOT.html
+
+
+Bitstream — ``IO_HP_TOP``
+=========================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-IO_HP_TOP.html
+
+
+Bitstream — ``IO_HR_PAIR``
+==========================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-IO_HR_PAIR.html
+
+
+Bitstream — ``IO_HR_BOT``
+=========================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-IO_HR_BOT.html
+
+
+Bitstream — ``IO_HR_TOP``
+=========================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-IO_HR_TOP.html
+
+
 Bitstream — ``HCLK_IOI_HP``
 ===========================
 

diff --git a/prjcombine_ise_hammer/src/clk/virtex7.rs b/prjcombine_ise_hammer/src/clk/virtex7.rs
@@ -658,7 +658,29 @@ pub fn add_fuzzers<'a>(
                         ]);
                     }
                 }
-                // TODO more IDELAYCTRL things
+                fuzz_one!(ctx, "PRESENT", "1", [], [(mode "IDELAYCTRL")]);
+                fuzz_enum!(ctx, "HIGH_PERFORMANCE_MODE", ["FALSE", "TRUE"], [(mode "IDELAYCTRL")]);
+                fuzz_one!(ctx, "MODE", "DEFAULT", [
+                    (tile_mutex "IDELAYCTRL", "TEST"),
+                    (mode "IDELAYCTRL")
+                ], [
+                    (attr "IDELAYCTRL_EN", "DEFAULT"),
+                    (attr "BIAS_MODE", "2")
+                ]);
+                fuzz_one!(ctx, "MODE", "FULL_0", [
+                    (tile_mutex "IDELAYCTRL", "TEST"),
+                    (mode "IDELAYCTRL")
+                ], [
+                    (attr "IDELAYCTRL_EN", "ENABLE"),
+                    (attr "BIAS_MODE", "0")
+                ]);
+                fuzz_one!(ctx, "MODE", "FULL_1", [
+                    (tile_mutex "IDELAYCTRL", "TEST"),
+                    (mode "IDELAYCTRL")
+                ], [
+                    (attr "IDELAYCTRL_EN", "ENABLE"),
+                    (attr "BIAS_MODE", "1")
+                ]);
             }
             {
                 let ctx = FuzzCtx::new(session, backend, tile, "HCLK_IOI", TileBits::Hclk);
@@ -1125,6 +1147,15 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, bali_only: bool) {
                     ],
                     "NONE",
                 );
+                ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
+                ctx.collect_enum_bool(tile, bel, "HIGH_PERFORMANCE_MODE", "FALSE", "TRUE");
+                ctx.collect_enum_default(
+                    tile,
+                    bel,
+                    "MODE",
+                    &["DEFAULT", "FULL_0", "FULL_1"],
+                    "NONE",
+                );
             }
             {
                 let bel = "HCLK_IOI";

diff --git a/prjcombine_ise_hammer/src/fgen.rs b/prjcombine_ise_hammer/src/fgen.rs
@@ -4375,29 +4375,19 @@ impl ExtraFeatureKind {
                 }
                 ExpandedDevice::Virtex2(_) => todo!(),
                 ExpandedDevice::Spartan6(_) => todo!(),
-                ExpandedDevice::Virtex4(edev) => match edev.kind {
-                    prjcombine_virtex4::grid::GridKind::Virtex4 => todo!(),
-                    prjcombine_virtex4::grid::GridKind::Virtex5 => {
-                        let node = backend.egrid.db.get_node(tile);
-                        backend.egrid.node_index[node]
-                            .iter()
-                            .map(|loc| vec![edev.btile_main(loc.0, loc.1, loc.2)])
-                            .collect()
-                    }
-                    prjcombine_virtex4::grid::GridKind::Virtex6 => {
-                        let node = backend.egrid.db.get_node(tile);
-                        backend.egrid.node_index[node]
-                            .iter()
-                            .map(|loc| {
-                                vec![
-                                    edev.btile_main(loc.0, loc.1, loc.2),
-                                    edev.btile_main(loc.0, loc.1, loc.2 + 1),
-                                ]
-                            })
-                            .collect()
-                    }
-                    prjcombine_virtex4::grid::GridKind::Virtex7 => todo!(),
-                },
+                ExpandedDevice::Virtex4(edev) => {
+                    let node = backend.egrid.db.get_node(tile);
+                    backend.egrid.node_index[node]
+                        .iter()
+                        .map(|loc| {
+                            backend.egrid.db.nodes[node]
+                                .tiles
+                                .ids()
+                                .map(|ti| edev.btile_main(loc.0, loc.1, loc.2 + ti.to_idx()))
+                                .collect()
+                        })
+                        .collect()
+                }
                 ExpandedDevice::Ultrascale(_) => todo!(),
                 ExpandedDevice::Versal(_) => todo!(),
             },

diff --git a/prjcombine_ise_hammer/src/io.rs b/prjcombine_ise_hammer/src/io.rs
@@ -5,4 +5,5 @@ pub mod virtex2;
 pub mod virtex4;
 pub mod virtex5;
 pub mod virtex6;
+pub mod virtex7;
 pub mod xc5200;
diff --git a/prjcombine_ise_hammer/src/io/virtex6.rs b/prjcombine_ise_hammer/src/io/virtex6.rs
@@ -510,26 +510,6 @@ pub fn add_fuzzers<'a>(
         fuzz_multi_attr_bin!(ctx, "INIT_PIPE_DATA0", 12, [(mode "OSERDESE1")]);
         fuzz_multi_attr_bin!(ctx, "INIT_PIPE_DATA1", 12, [(mode "OSERDESE1")]);
 
-        // TODO OLOGIC
-        // - TFFTYPE  DDR #LATCH #FF
-        // - OUTFFTYPE  DDR #LATCH #FF
-        // - TMUX  T1 TFF
-        // - OMUX  D1 OUTFF
-        // - T1USED  0
-        // - O1USED  0
-        // - TQUSED  0
-        // - OQUSED  0
-        // - TFBUSED  0
-        // - OFBUSED  0
-
-        // TODO OSERDES
-        // - DATA_RATE_OQ  SDR DDR
-        // - DATA_RATE_TQ  SDR DDR BUF
-        // - DATA_WIDTH  2 3 4 5 6 7 8 10
-        // - INTERFACE_TYPE  DEFAULT MEMORY_DDR3
-
-        // TODO: OLOGIC
-
         for (src, num) in [("HCLK", 12), ("RCLK", 6)] {
             for j in 0..num {
                 fuzz_one!(ctx, "MUX.CLKDIV", format!("{src}{j}"), [
@@ -1526,8 +1506,6 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, devdata_only: bool) {
         ctx.tiledb.insert(tile, bel, "OFF_SR_USED", osrused);
         ctx.tiledb.insert(tile, bel, "TFF_SR_USED", tsrused);
 
-        // TODO: OLOGIC
-
         let mut diffs = vec![];
         for val in ["2", "3", "4", "5", "6", "7", "8"] {
             diffs.push((