xact_dump with xc4000 and xc5200

prjunnamed · Nov 21, 2024 · cd315e0 · cd315e0
1 parent c1cd91e
commit cd315e0
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diff --git a/Cargo.toml b/Cargo.toml
@@ -60,6 +60,12 @@ members = [
 	"prjcombine_hammer",
 	"prjcombine_collector",
 	"prjcombine_ise_hammer",
+	"prjcombine_xact_naming",
+	"prjcombine_xc4000_xact",
+	"prjcombine_xc5200_xact",
+	"prjcombine_xact_data",
+	"prjcombine_xact_dump",
+	"prjcombine_xact_geom",
 	"prjcombine_vm6",
 	"prjcombine_xilinx_cpld",
 	"prjcombine_xilinx_recpld",
@@ -129,6 +135,11 @@ prjcombine_lattice_rawdump = { path = "prjcombine_lattice_rawdump" }
 prjcombine_virtex_bitstream = { path = "prjcombine_virtex_bitstream" }
 prjcombine_hammer = { path = "prjcombine_hammer" }
 prjcombine_collector = { path = "prjcombine_collector" }
+prjcombine_xact_naming = { path = "prjcombine_xact_naming" }
+prjcombine_xc4000_xact = { path = "prjcombine_xc4000_xact" }
+prjcombine_xc5200_xact = { path = "prjcombine_xc5200_xact" }
+prjcombine_xact_geom = { path = "prjcombine_xact_geom" }
+prjcombine_xact_data = { path = "prjcombine_xact_data" }
 prjcombine_vm6 = { path = "prjcombine_vm6" }
 prjcombine_xilinx_cpld = { path = "prjcombine_xilinx_cpld" }
 prjcombine_ise_dump = { path = "prjcombine_ise_dump" }
@@ -162,6 +173,7 @@ bimap = "0.6"
 std-semaphore = "0.1"
 which = "7"
 derive-where = "1.2"
+bytes = "1.8.0"
 hex = "0.4.3"
 des = "0.8.1"
 cbc = "0.1.2"

diff --git a/databases/xc4ke-tiledb.json b/databases/xc4ke-tiledb.json
diff --git a/databases/xc4kex-tiledb.json b/databases/xc4kex-tiledb.json
diff --git a/databases/xc4kxla-tiledb.json b/databases/xc4kxla-tiledb.json
diff --git a/databases/xc4kxv-tiledb.json b/databases/xc4kxv-tiledb.json
diff --git a/databases/xcsxl-tiledb.json b/databases/xcsxl-tiledb.json
diff --git a/prjcombine_int/src/db.rs b/prjcombine_int/src/db.rs
@@ -53,7 +53,7 @@ entity_id! {
     pub id BelId u16, reserve 1;
 }
 
-#[derive(Clone, Debug, Serialize, Deserialize)]
+#[derive(Clone, Debug, Default, PartialEq, Eq, Serialize, Deserialize)]
 pub struct IntDb {
     pub wires: EntityMap<WireId, String, WireKind>,
     pub nodes: EntityMap<NodeKindId, String, NodeKind>,
@@ -131,7 +131,7 @@ pub enum MuxKind {
     OptInv,
 }
 
-#[derive(Clone, Debug, Eq, PartialEq, Serialize, Deserialize)]
+#[derive(Clone, Debug, Eq, PartialEq, Default, Serialize, Deserialize)]
 pub struct BelInfo {
     pub pins: BTreeMap<String, BelPin>,
 }

diff --git a/prjcombine_int/src/grid.rs b/prjcombine_int/src/grid.rs
@@ -444,6 +444,47 @@ impl ExpandedGrid<'_> {
         }
     }
 
+    pub fn resolve_wire_nobuf(&self, mut wire: IntWire) -> Option<IntWire> {
+        let die = self.die(wire.0);
+        loop {
+            let tile = die.tile(wire.1);
+            let wi = self.db.wires[wire.2];
+            match wi {
+                WireKind::ClkOut(_) => {
+                    wire.1 = tile.clkroot;
+                    break;
+                }
+                WireKind::MultiBranch(dir) | WireKind::Branch(dir) | WireKind::PipBranch(dir) => {
+                    if let Some(t) = &tile.terms[dir] {
+                        let term = &self.db.terms[t.kind];
+                        match term.wires.get(wire.2) {
+                            Some(&TermInfo::BlackHole) => return None,
+                            Some(&TermInfo::PassNear(wf)) => {
+                                wire.2 = wf;
+                            }
+                            Some(&TermInfo::PassFar(wf)) => {
+                                wire.1 = t.target.unwrap();
+                                wire.2 = wf;
+                            }
+                            None => break,
+                        }
+                    } else {
+                        break;
+                    }
+                }
+                _ => break,
+            }
+        }
+        if let Some(&twire) = self.xdie_wires.get_by_left(&wire) {
+            wire = twire;
+        }
+        if self.blackhole_wires.contains(&wire) {
+            None
+        } else {
+            Some(wire)
+        }
+    }
+
     pub fn wire_tree(&self, wire: IntWire) -> Vec<IntWire> {
         if self.blackhole_wires.contains(&wire) {
             return vec![];

diff --git a/prjcombine_ise_hammer/src/gt/virtex4.rs b/prjcombine_ise_hammer/src/gt/virtex4.rs
@@ -2,7 +2,10 @@ use prjcombine_collector::{
     xlat_bit, xlat_bitvec, xlat_enum, xlat_enum_default, xlat_enum_ocd, Diff, OcdMode,
 };
 use prjcombine_hammer::Session;
-use prjcombine_int::{db::{BelId, Dir}, grid::DieId};
+use prjcombine_int::{
+    db::{BelId, Dir},
+    grid::DieId,
+};
 use prjcombine_types::tiledb::{TileBit, TileItem};
 use prjcombine_xilinx_geom::ExpandedDevice;
 use unnamed_entity::EntityId;

diff --git a/prjcombine_ise_hammer/src/int/xc4000.rs b/prjcombine_ise_hammer/src/int/xc4000.rs
@@ -926,7 +926,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             }
             if out_name == "IMUX.TBUF0.I"
                 || out_name == "IMUX.TBUF1.I"
-                || ((out_name == "IMUX.IOB0.CE" || out_name == "IMUX.IOB1.CE")
+                || ((out_name == "IMUX.IOB0.O1" || out_name == "IMUX.IOB1.O1")
                     && tile.starts_with("IO"))
             {
                 assert!(!got_empty);
@@ -936,7 +936,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
 
             for (rtile, rwire, rbel, rattr) in [
                 ("CNR.BL", "IMUX.IOB1.IK", "MD1", "ENABLE.T"),
-                ("CNR.BL", "IMUX.IOB1.CE", "MD1", "ENABLE.O"),
+                ("CNR.BL", "IMUX.IOB1.O1", "MD1", "ENABLE.O"),
                 ("CNR.BL", "IMUX.RDBK.TRIG", "RDBK", "ENABLE"),
                 ("CNR.BR", "IMUX.STARTUP.GTS", "STARTUP", "ENABLE.GTS"),
                 ("CNR.BR", "IMUX.STARTUP.GSR", "STARTUP", "ENABLE.GSR"),

diff --git a/prjcombine_ise_hammer/src/misc/virtex4.rs b/prjcombine_ise_hammer/src/misc/virtex4.rs
@@ -1,7 +1,10 @@
 use bitvec::prelude::*;
 use prjcombine_collector::{xlat_bit, xlat_bitvec, xlat_enum_ocd, xlat_item_tile, Diff, OcdMode};
 use prjcombine_hammer::Session;
-use prjcombine_int::{db::{BelId, Dir}, grid::DieId};
+use prjcombine_int::{
+    db::{BelId, Dir},
+    grid::DieId,
+};
 use prjcombine_types::tiledb::{TileBit, TileItem, TileItemKind};
 use prjcombine_virtex_bitstream::Reg;
 use prjcombine_xilinx_geom::ExpandedDevice;

diff --git a/prjcombine_ultrascale/src/expand.rs b/prjcombine_ultrascale/src/expand.rs
@@ -9,7 +9,8 @@ use unnamed_entity::{EntityId, EntityPartVec, EntityVec};
 
 use crate::expanded::{ClkSrc, ExpandedDevice, GtCoord, HdioCoord, HpioCoord, IoCoord};
 use crate::grid::{
-    CleMKind, ColSide, Column, ColumnKindLeft, ColumnKindRight, DisabledPart, DspKind, Grid, GridKind, HardRowKind, HdioIobId, HpioIobId, Interposer, IoRowKind, RegId
+    CleMKind, ColSide, Column, ColumnKindLeft, ColumnKindRight, DisabledPart, DspKind, Grid,
+    GridKind, HardRowKind, HdioIobId, HpioIobId, Interposer, IoRowKind, RegId,
 };
 
 use crate::bond::SharedCfgPin;

diff --git a/prjcombine_ultrascale/src/expanded.rs b/prjcombine_ultrascale/src/expanded.rs
@@ -6,7 +6,8 @@ use std::collections::BTreeSet;
 use unnamed_entity::{EntityId, EntityPartVec, EntityVec};
 
 use crate::grid::{
-    ColSide, ColumnKindRight, DisabledPart, Grid, GridKind, HardRowKind, HdioIobId, HpioIobId, Interposer, IoRowKind, RegId
+    ColSide, ColumnKindRight, DisabledPart, Grid, GridKind, HardRowKind, HdioIobId, HpioIobId,
+    Interposer, IoRowKind, RegId,
 };
 
 use crate::bond::SharedCfgPin;

diff --git a/prjcombine_ultrascale_rd2db/src/grid.rs b/prjcombine_ultrascale_rd2db/src/grid.rs
@@ -1,7 +1,9 @@
 use prjcombine_int::grid::{ColId, DieId, RowId};
 use prjcombine_rawdump::{Coord, NodeId, Part, TkSiteSlot};
 use prjcombine_ultrascale::grid::{
-    BramKind, CleLKind, CleMKind, ColSide, Column, ColumnKindLeft, ColumnKindRight, DisabledPart, DspKind, Grid, GridKind, HardColumn, HardKind, HardRowKind, HdioIobId, HpioIobId, Interposer, IoColumn, IoRowKind, Ps, PsIntfKind, RegId
+    BramKind, CleLKind, CleMKind, ColSide, Column, ColumnKindLeft, ColumnKindRight, DisabledPart,
+    DspKind, Grid, GridKind, HardColumn, HardKind, HardRowKind, HdioIobId, HpioIobId, Interposer,
+    IoColumn, IoRowKind, Ps, PsIntfKind, RegId,
 };
 use prjcombine_ultrascale_naming::DeviceNaming;
 use std::collections::{BTreeMap, BTreeSet, HashSet};
@@ -293,9 +295,7 @@ fn get_cols_hard(
                 y: y as u16,
             };
             let tile = &int.rd.tiles[&crd];
-            if tile.sites.iter().next().is_none()
-                && tt != "DFE_DFE_TILEG_FT"
-            {
+            if tile.sites.iter().next().is_none() && tt != "DFE_DFE_TILEG_FT" {
                 disabled.insert(DisabledPart::HardIp(dieid, col, reg));
             }
             if tt == "HDIO_BOT_RIGHT" {
@@ -839,9 +839,7 @@ pub fn make_grids(
         }
     }
     let primary = DieId::from_idx(primary.unwrap());
-    let interposer = Interposer {
-        primary,
-    };
+    let interposer = Interposer { primary };
     if grids.first().unwrap().ps.is_some() {
         let mut found = false;
         for pins in rd.packages.values() {

diff --git a/prjcombine_versal_rd2db/src/int.rs b/prjcombine_versal_rd2db/src/int.rs
@@ -1,10 +1,10 @@
 use enum_map::EnumMap;
 use prjcombine_int::db::{Dir, IntDb, NodeTileId, TermInfo, TermKind, WireKind};
 use prjcombine_rawdump::{Part, TkWire};
+use prjcombine_versal_naming::DeviceNaming;
 use prjcombine_versal_naming::{
     BUFDIV_LEAF_SWZ_A, BUFDIV_LEAF_SWZ_AH, BUFDIV_LEAF_SWZ_B, BUFDIV_LEAF_SWZ_BH,
 };
-use prjcombine_versal_naming::DeviceNaming;
 use prjcombine_xilinx_naming::db::NamingDb;
 use std::collections::HashMap;
 use unnamed_entity::{EntityId, EntityPartVec};

diff --git a/prjcombine_versal_rdverify/src/lib.rs b/prjcombine_versal_rdverify/src/lib.rs
@@ -395,7 +395,11 @@ fn verify_bufdiv_leaf(vrf: &mut Verifier, bel: &BelContext<'_>) {
     }
 }
 
-fn verify_rclk_hdistr_loc(_endev: &ExpandedNamedDevice, _vrf: &mut Verifier, _bel: &BelContext<'_>) {
+fn verify_rclk_hdistr_loc(
+    _endev: &ExpandedNamedDevice,
+    _vrf: &mut Verifier,
+    _bel: &BelContext<'_>,
+) {
     // XXX verify HDISTR_LOC
 }
 
@@ -494,7 +498,8 @@ fn verify_bufgce_hdio(vrf: &mut Verifier, bel: &BelContext<'_>) {
 fn verify_dpll_hdio(endev: &ExpandedNamedDevice, vrf: &mut Verifier, bel: &BelContext<'_>) {
     let grid = endev.edev.grids[bel.die];
     let reg = grid.row_to_reg(bel.row);
-    if !endev.edev
+    if !endev
+        .edev
         .disabled
         .contains(&DisabledPart::HdioDpll(bel.die, bel.col, reg))
     {

diff --git a/prjcombine_virtex4/src/expand.rs b/prjcombine_virtex4/src/expand.rs
@@ -20,8 +20,6 @@ pub fn expand_grid<'a>(
         GridKind::Virtex4 => virtex4::expand_grid(grids, disabled, db),
         GridKind::Virtex5 => virtex5::expand_grid(grids, disabled, db),
         GridKind::Virtex6 => virtex6::expand_grid(grids, disabled, db),
-        GridKind::Virtex7 => {
-            virtex7::expand_grid(grids, interposer.unwrap(), disabled, db)
-        }
+        GridKind::Virtex7 => virtex7::expand_grid(grids, interposer.unwrap(), disabled, db),
     }
 }
diff --git a/prjcombine_virtex4/src/expand/virtex7.rs b/prjcombine_virtex4/src/expand/virtex7.rs
@@ -9,7 +9,7 @@ use unnamed_entity::{EntityId, EntityPartVec, EntityVec};
 
 use crate::bond::SharedCfgPin;
 use crate::expanded::{DieFrameGeom, ExpandedDevice, Gtz, IoCoord, TileIobId};
-use crate::grid::{ColumnKind, DisabledPart, Interposer, Grid, GtKind, GtzLoc, IoKind, Pcie2Kind};
+use crate::grid::{ColumnKind, DisabledPart, Grid, GtKind, GtzLoc, Interposer, IoKind, Pcie2Kind};
 
 struct DieExpander<'a, 'b, 'c> {
     grid: &'b Grid,

diff --git a/prjcombine_virtex7_rd2db/src/grid.rs b/prjcombine_virtex7_rd2db/src/grid.rs
@@ -1,7 +1,7 @@
 use prjcombine_int::grid::{ColId, DieId, RowId};
 use prjcombine_rawdump::{Coord, Part};
 use prjcombine_virtex4::grid::{
-    ColumnKind, DisabledPart, Interposer, Grid, GridKind, GtColumn, GtKind, IoColumn, IoKind,
+    ColumnKind, DisabledPart, Grid, GridKind, GtColumn, GtKind, Interposer, IoColumn, IoKind,
     Pcie2, Pcie2Kind, RegId,
 };
 use std::collections::BTreeSet;
@@ -268,13 +268,7 @@ fn get_cols_gt(int: &IntGrid, columns: &EntityVec<ColId, ColumnKind>) -> Vec<GtC
     res
 }
 
-pub fn make_grids(
-    rd: &Part,
-) -> (
-    EntityVec<DieId, Grid>,
-    Interposer,
-    BTreeSet<DisabledPart>,
-) {
+pub fn make_grids(rd: &Part) -> (EntityVec<DieId, Grid>, Interposer, BTreeSet<DisabledPart>) {
     let mut rows_slr_split: BTreeSet<_> = find_rows(rd, &["B_TERM_INT_SLV"])
         .into_iter()
         .map(|x| x as u16)

diff --git a/prjcombine_xact_data/Cargo.toml b/prjcombine_xact_data/Cargo.toml
@@ -0,0 +1,16 @@
+[package]
+name = "prjcombine_xact_data"
+edition.workspace = true
+version.workspace = true
+
+[dependencies]
+bytes.workspace = true
+ndarray.workspace = true
+regex.workspace = true
+enum-map.workspace = true
+clap.workspace = true
+unnamed_entity.workspace = true
+prjcombine_int.workspace = true
+
+[lints]
+workspace = true
diff --git a/prjcombine_xact_data/src/bin/dump_xact_die.rs b/prjcombine_xact_data/src/bin/dump_xact_die.rs
@@ -0,0 +1,94 @@
+use std::path::PathBuf;
+
+use clap::Parser;
+use prjcombine_xact_data::die::Die;
+
+#[derive(Parser)]
+struct Args {
+    xact: PathBuf,
+    part: String,
+}
+
+fn main() {
+    let args = Args::parse();
+    let die = Die::parse(&args.xact, &args.part);
+    let matrix = die.make_unified_matrix();
+    for row in (0..matrix.dim().1).rev() {
+        for col in 0..matrix.dim().0 {
+            let c = matrix[(col, row)];
+            let (g, c) = match c & 0xff {
+                _ if (c & 0x3f) == 9 => ('M', 'Y'),
+                0x31 => ('O', 'Y'),
+                0x35 => ('I', 'Y'),
+                0x39 => (' ', ' '),
+                0x11 => ('─', 'P'),
+                0x15 => ('│', 'P'),
+                0x18 => ('│', 'W'),
+                0x58 => ('─', 'W'),
+                0x10 => ('┬', 'W'),
+                0x50 => ('┤', 'W'),
+                0x90 => ('┴', 'W'),
+                0xd0 => ('├', 'W'),
+                0x14 => ('└', 'W'),
+                0x54 => ('┌', 'W'),
+                0x94 => ('┐', 'W'),
+                0xd4 => ('┘', 'W'),
+                0x0c => ('┼', 'W'),
+
+                0x28 => ('│', 'B'),
+                0x68 => ('─', 'B'),
+                0x2b => ('V', 'R'),
+                0x2a => ('^', 'R'),
+                0x6b => ('<', 'G'),
+                0x6a => ('>', 'G'),
+
+                0x20 => ('┬', 'B'),
+                0x60 => ('┤', 'B'),
+                0xa0 => ('┴', 'B'),
+                0xe0 => ('├', 'B'),
+                0x22 => ('┬', 'R'),
+                0x62 => ('┤', 'G'),
+                0xa2 => ('┴', 'R'),
+                0xe2 => ('├', 'G'),
+                0x23 => ('┬', 'G'),
+                0x63 => ('┤', 'R'),
+                0xa3 => ('┴', 'G'),
+                0xe3 => ('├', 'R'),
+
+                0x24 => ('└', 'B'),
+                0x64 => ('┌', 'B'),
+                0xa4 => ('┐', 'B'),
+                0xe4 => ('┘', 'B'),
+                0x26 => ('└', 'R'),
+                0x66 => ('┌', 'G'),
+                0xa6 => ('┐', 'R'),
+                0xe6 => ('┘', 'G'),
+                0x27 => ('└', 'G'),
+                0x67 => ('┌', 'R'),
+                0xa7 => ('┐', 'G'),
+                0xe7 => ('┘', 'R'),
+
+                0x2c => ('┼', 'B'),
+                0x2e => ('┼', 'R'),
+                0x2f => ('┼', 'G'),
+
+                _ => panic!("umm {c}"),
+            };
+            match c {
+                ' ' => (),
+                'W' => print!("\x1b[1m"),
+                'R' => print!("\x1b[31;1m"),
+                'G' => print!("\x1b[32;1m"),
+                'B' => print!("\x1b[34;1m"),
+                'P' => print!("\x1b[35;1m"),
+                'Y' => print!("\x1b[33;1m"),
+                _ => unreachable!(),
+            }
+            print!("{g}");
+            if c != ' ' {
+                print!("\x1b[0m");
+            }
+        }
+        println!();
+    }
+}