Deploying to gh-pages from @ 501a212 🚀

_sources/xilinx/index.rst.txt

@@ -5,6 +5,11 @@ Xilinx FPGAs
    :maxdepth: 2
    :caption: Contents:
 
+   xc4000e/index
+   xc4000ex/index
+   xc4000xla/index
+   xc4000xv/index
+   spartanxl/index
    xc5200/index
    virtex/index
    virtex2/index

_sources/xilinx/spartanxl/clb.rst.txt

@@ -0,0 +1,65 @@
+Configurable Logic Block
+########################
+
+
+``CLB``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.html
+
+
+``CLB.L``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.L.html
+
+
+``CLB.R``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.R.html
+
+
+``CLB.B``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.B.html
+
+
+``CLB.LB``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.LB.html
+
+
+``CLB.RB``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.RB.html
+
+
+``CLB.T``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.T.html
+
+
+``CLB.LT``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.LT.html
+
+
+``CLB.RT``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CLB.RT.html

_sources/xilinx/spartanxl/corner.rst.txt

@@ -0,0 +1,30 @@
+Corners
+#######
+
+
+``CNR.BL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CNR.BL.html
+
+
+``CNR.TL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CNR.TL.html
+
+
+``CNR.BR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CNR.BR.html
+
+
+``CNR.TR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-CNR.TR.html

_sources/xilinx/spartanxl/index.rst.txt

@@ -0,0 +1,14 @@
+Spartan XL
+##########
+
+.. todo:: intro document, bitstream format, other tiles, jtag, ...
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   clb
+   io
+   corner
+   splitter
+

_sources/xilinx/spartanxl/io.rst.txt

@@ -0,0 +1,114 @@
+Input/Output
+############
+
+
+``IO.L``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.L.html
+
+
+``IO.L.T``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.L.T.html
+
+
+``IO.LS``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.LS.html
+
+
+``IO.LS.B``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.LS.B.html
+
+
+``IO.R``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.R.html
+
+
+``IO.R.T``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.R.T.html
+
+
+``IO.RS``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.RS.html
+
+
+``IO.RS.B``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.RS.B.html
+
+
+``IO.B``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.B.html
+
+
+``IO.B.R``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.B.R.html
+
+
+``IO.BS``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.BS.html
+
+
+``IO.BS.L``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.BS.L.html
+
+
+``IO.T``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.T.html
+
+
+``IO.T.R``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.T.R.html
+
+
+``IO.TS``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.TS.html
+
+
+``IO.TS.L``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-IO.TS.L.html

_sources/xilinx/spartanxl/splitter.rst.txt

@@ -0,0 +1,51 @@
+Splitters
+#########
+
+
+``LLH.CLB``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLH.CLB.html
+
+
+``LLH.CLB.B``
+=============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLH.CLB.B.html
+
+
+``LLH.IO.B``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLH.IO.B.html
+
+
+``LLH.IO.T``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLH.IO.T.html
+
+
+``LLV.CLB``
+===========
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLV.CLB.html
+
+
+``LLV.IO.L``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLV.IO.L.html
+
+
+``LLV.IO.R``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xcsxl-LLV.IO.R.html

_sources/xilinx/xc4000e/clb.rst.txt

@@ -0,0 +1,65 @@
+Configurable Logic Block
+########################
+
+
+``CLB``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.html
+
+
+``CLB.L``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.L.html
+
+
+``CLB.R``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.R.html
+
+
+``CLB.B``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.B.html
+
+
+``CLB.LB``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.LB.html
+
+
+``CLB.RB``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.RB.html
+
+
+``CLB.T``
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.T.html
+
+
+``CLB.LT``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.LT.html
+
+
+``CLB.RT``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CLB.RT.html

_sources/xilinx/xc4000e/corner.rst.txt

@@ -0,0 +1,30 @@
+Corners
+#######
+
+
+``CNR.BL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CNR.BL.html
+
+
+``CNR.TL``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CNR.TL.html
+
+
+``CNR.BR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CNR.BR.html
+
+
+``CNR.TR``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xc4ke-CNR.TR.html