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PyMTL4.0 Release #264

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PyMTL4.0 Release #264

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@ptpan ptpan commented Jan 29, 2024 •
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This PR includes changes that will be part of the PyMTL 4.0 release. Here is a list of changes included in this PR (WIP):

  • Support for Verilator 5.016, including Verilog import support and CI setup
  • Revamped Verilog import support to address data corruption / segfaults
  • Support for parallel pytest runs with the xdist module
  • Support for Verilator assertion

ptpan and others added 30 commits November 23, 2023 14:21
@ptpan
Rename basic_rtl to primitive
488093e
@ptpan
[WIP] Stream and dstruct
6584709
@ptpan
[WIP] StreamSrc/Sink test passing
60d73b5
@ptpan
[WIP] example and stdlib unit tests passing
5778a40
@ptpan
[WIP] Remove out dated tests
686db8c
@ptpan
Remove TestMasterCL
6f12baf
@ptpan
Add back the RTL-FL adapters
406ff8c
@ptpan
Split adapter implementation into single files
bed393f
@ptpan
Hold stream source when current message is None
519c711
@ptpan
Add line_trace to I/OStreamIfc
25c3751
@ptpan
[ProcFL] Add back ProcFL with adapters
b72cdea
@cbatten @ptpan
get tests running on ProcFL
3a6a375
@cbatten @ptpan
forgot to commit this update
9834cc8
@cbatten @ptpan
add random delays to src/sink
4f5a8b1
@ptpan
[dev] Add py module to dependency
a70db04
@cbatten @ptpan
add ordered option to stream sink
6db6cee
@cbatten @ptpan
temporary fix to change mem msg type field to 3bits
326559e
@ptpan
Fixing double/single underscore issue in translation
37882bc
@ptpan
Add non-blocking stream FL adapters
0e81097
@ptpan
Exposing stream-to-FL adapters in stdlib.stream
0eab5e3
@ptpan
Add line trace to stream-to-FL adapters
85300ff
@ptpan
[mem] Add INV and FLUSH support to MemoryFL
661c0bd
@ptpan
[mem] Add error message to out-of-bound accesses
86500e9
@ptpan
[verilator] Force signals to toggle on posedge CLK
8c961c7
@ptpan
[verilator] Add support for verilator 4.228
a27b176
@ptpan
[verilator] Update use of verilator variable name in C wrapper
77e708d
@ptpan
[test] Fix segfault due to same toplevel name
cf51f50
@ptpan
[test] Temporarily disable tests in yosys backend
d628f6a
@ptpan
[mem] Improve error messages for behavioral mem
151edf5
@ptpan
[error msg] Add error messages for double configuring a model
fdaaad2
ptpan and others added 13 commits December 6, 2023 16:57
@ptpan
Merge pull request #260 from pymtl/pp482-construct-self
0738bb7 
Add support for non-s args to refer to self
@ptpan
[yosys] Deprecate yosys backend
0be16f7
@ptpan
[coverage] Disable couldnt-parse coverage warning
512557d
@ptpan
[test] Remove return values from mamba unit tests
58ea59a
@ptpan
[import] Fix data type declaration for signals of different widths
7e55309
@ptpan
[setup] Add fasteners to dependency
7ce58d5
@ptpan
[import] Use explicitly sized uint types for signal declaration
c8e2ab5
@ptpan
[rtlir] Add visit_Constant to behavioral visitor
aa19bfb
@ptpan
[test] Use variable instead of int in extslice test case
824ee65
@ptpan
[test] Fix visit_Str test
6da7397
@ptpan
[import] Add an import test that uses assertion
1bf1b7d
@ptpan
[import] Implement Verilator assertion failure without aborting process
25c0752
@ptpan
[import] Fix a bug in Verilog trace of generators
adc9056
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codecov bot commented Jan 29, 2024 •
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Codecov Report

Attention: Patch coverage is 91.41717% with 172 lines in your changes missing coverage. Please review.

Project coverage is 89.83%. Comparing base (fc7c3fa) to head (198430b).
Report is 2 commits behind head on master.

❗ Current head 198430b differs from pull request most recent head 07b3bbb

Please upload reports for the commit 07b3bbb to get more accurate results.

Files Patch % Lines
pymtl3/stdlib/mem/MemRequesterAdapterFL.py 18.18% 45 Missing ⚠️
pymtl3/stdlib/xcel/XcelRequesterAdapterFL.py 18.18% 36 Missing ⚠️
pymtl3/stdlib/stream/OStreamEnqAdapterFL.py 28.57% 15 Missing ⚠️
pymtl3/stdlib/stream/IStreamDeqAdapterFL.py 35.29% 11 Missing ⚠️
...ends/verilog/import_/VerilogVerilatorImportPass.py 85.29% 10 Missing ⚠️
...asses/rtlir/behavioral/BehavioralRTLIRGenL1Pass.py 30.00% 7 Missing ⚠️
...sses/rtlir/structural/StructuralRTLIRSignalExpr.py 75.00% 6 Missing ⚠️
pymtl3/stdlib/test_utils/test_helpers.py 50.00% 5 Missing ⚠️
.../passes/backends/verilog/VerilogPlaceholderPass.py 0.00% 4 Missing ⚠️
pymtl3/stdlib/mem/MemoryFL.py 87.87% 4 Missing ⚠️
... and 15 more
Additional details and impacted files 
@@            Coverage Diff             @@
##           master     #264      +/-   ##
==========================================
+ Coverage   89.18%   89.83%   +0.65%     
==========================================
  Files         330      317      -13     
  Lines       30440    28271    -2169     
==========================================
- Hits        27147    25398    -1749     
+ Misses       3293     2873     -420

☔ View full report in Codecov by Sentry.
📢 Have feedback on the report? Share it here.

ptpan and others added 16 commits February 6, 2024 14:34
@ptpan
[test] Fix bitstruct hypothesis test
8c04957
@ptpan
[pytest] Skip yosys tests by default
84621d2
@ptpan
[ci] Add new Python versions and remove 3.6
86952f5
@ptpan
[ci] Update to checkout@v4 and setup-python@v5
6cfd5b3
@KelvinChung2000
Adding __len__ interface and formatting to black
b8c71b8
@KelvinChung2000
Undo formatting
6cf12f8
@KelvinChung2000
add test
22230dd
@yo96
Add new line at end of file
49bfcb1
@yo96
Remove trailing white spaces.
d5bf3ba
@yo96
Merge pull request #272 from KelvinChung2000/len-interface
198430b 
Adding __len__ interface
@cbatten
Fix issue with pytest_cmdline_preparse
2eb57d3 
The pytest_cmdline_preparse hook is now deprecated. I think there should
be a way to achieve the same effect using pytest_load_initial_conftests

https://docs.pytest.org/en/7.1.x/reference/reference.html#pytest.hookspec.pytest_cmdline_preparse

However, were were using this to hook to prevent *.pyc and __pycache__
files from being generated. I think it is fine for now to just go back
to generating these files.
@KelvinChung2000
Improve index handling in Bits and Signal classes
b39d505
@KelvinChung2000
Adding test
d0bc16e
@KelvinChung2000
update ast helper
05d82ac
@yo96
Merge pull request #275 from KelvinChung2000/improve-indexing
07b3bbb 
Improve index handling in Bits and Signal classes
@cbatten
Verilator now requires C++14
ea01547
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4 participants
@ptpan @cbatten @KelvinChung2000 @yo96