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Imperas Risc-V OVPsim Release v20200330.0
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@Imperas Imperas released this 21 May 19:48
· 26 commits to master since this release
v20200330.0
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riscvOVPsim Change Log

Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com

This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model

Date 2020-March-31
Release 20200330.0

  • The priority order for handling simultaneous interrupts destined for the
    same privilege level has been corrected (previously, these were handled so
    that higher interrupt numbers were higher priority).
  • Some Vector Extension issues have been corrected:
    • All vector floating point instructions now generate Illegal Instruction
      exceptions if the current rounding mode is invalid, even if those
      instructions do not use the rounding mode.
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