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Support for smp in multiple DMs #910

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Support for smp in multiple DMs #910

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dd753a8
Support for smp in multiple DMs by dealing with riscv hartid and inde…
lz-bro Aug 28, 2023
b38a9e8
Merge branch 'riscv:riscv' into riscv
lz-bro Sep 21, 2023
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5 changes: 4 additions & 1 deletion src/target/riscv/riscv-013.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1897,7 +1897,6 @@ static int examine(struct target *target)

riscv013_info_t *info = get_info(target);

info->index = target->coreid;
info->abits = get_field(dtmcontrol, DTM_DTMCS_ABITS);
info->dtmcs_idle = get_field(dtmcontrol, DTM_DTMCS_IDLE);

Expand Down Expand Up @@ -2031,6 +2030,10 @@ static int examine(struct target *target)
return ERROR_FAIL;
}

/* The RISC-V hartid is sequential, and the index of each hart
* on the Debug Module should start at 0 and be contiguous. */
info->index = target->coreid % dm->hart_count;
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Doesn't this assume that each DM has the same number of harts?

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@lz-bro lz-bro Aug 31, 2023 •
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Thanks for your reminder, I didn't consider the situation that each DM has different number of harts, if this situation happens, user configuration will become unfriendly. So I currently have two ideas to solve it:
Config modification
config like

# cluster 0
target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -index 0 -rtos hwthread
target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -index 1

# cluster 1
target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 -index 0 -dbgbase 0x400 -rtos hwthread
target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 -index 1 -dbgbase 0x400

target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3

Modify the 'jim_target_create' function to get the target->index.

info->index get
https://github.com/riscv/riscv-openocd/blob/699eecaab434337dc3915171606b0548c48c6d51/src/target/riscv/riscv-013.c#L1900
changed to

info->index = target->index;

Get different threadids through hartid
config like

# cluster 0
target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1

# cluster 1
target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -dbgbase 0x400 -rtos hwthread
target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -dbgbase 0x400

target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3

Make appropriate modifications to the "threadid_from_target' function, I still don’t know how to modify it

static inline threadid_t threadid_from_target(const struct target *target)
{
	#return target->coreid + 1;
        ...
}

thread id should be 0/1/2/3


/* Don't call any riscv_* functions until after we've counted the number of
* cores and initialized registers. */

Expand Down