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BF16 tests #395
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BF16 tests #395
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Please change this as a pull into the dev branch instead of the main branch to avoid merge issues |
riscv-test-suite/env/arch_test.h
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#else | ||
#define FLREG flq | ||
#define FSREG fsq | ||
#define FREGWIDTH 16 | ||
#endif | ||
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#if ZFINX==1 | ||
#define FLREG ld |
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Can you explain why you are defining FLREG to be a 64b load for Zfinx? Note that this definition must also work for an RV32_Zfinx which doesn't implement ld, which is RV64 only
@adlr are you still working on BF16? I have closed your PR at ctg because of the conflicts with Zfa coverpoints. Please take a look at the coverpoints, also deliver the coverpoints and ACTs in a single PR. Apologies any inconvenience. |
Hi Umer, no worries at all! I haven't been working on BF16 for a while and I'm pretty preoccupied with a number of other things. If someone wants to take this over and make the changes, please do! |
Description
First cut of tests for BF16. I would like to get community feedback on these, either in this change or the other supporting changes:
riscv-software-src/riscv-isac#77
riscv-software-src/riscv-ctg#82
Related Issues
NA
Ratified/Unratified Extensions
List Extensions
Zfbfmin, Zvfbfmin Zvfbfwma
https://github.com/riscv/riscv-bfloat16/releases/download/20230629/riscv-bfloat16.pdf
Reference Model Used
Mandatory Checklist:
Optional Checklist: