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BF16 tests #395

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BF16 tests #395

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97c1521
Zfbfmin scalar tests
Sep 7, 2023
ee620c0
Zvfbfmin: ACT tests
Oct 4, 2023
158c34a
Zvfbfwma: First cut of tests
Oct 4, 2023
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57 changes: 55 additions & 2 deletions riscv-test-suite/env/test_macros.h
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Original file line number Diff line number Diff line change
Expand Up @@ -453,16 +453,69 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg)
csrr flagreg, fcsr ;\
)

#define TEST_FPSR_OP_VFWMACCBF16_VV( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \
LI(testreg, fcsr_val) ; \
csrw fcsr, testreg ; \
vmv.s.x v1, x0 ; \
vfmv.s.f v2, freg ; \
vfmv.s.f v3, freg ; \
inst v1, v2, v3 ; \
vfmv.f.s destreg, v1 ; \
csrr flagreg, fcsr ; \
)

#define TEST_FPSR_OP_VFWMACCBF16_VF( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \
LI(testreg, fcsr_val) ; \
csrw fcsr, testreg ; \
vmv.s.x v1, x0 ; \
vfmv.s.f v3, freg ; \
inst v1, freg, v3 ; \
vfmv.f.s destreg, v1 ; \
csrr flagreg, fcsr ; \
)

//Tests for floating-point instructions with a single register operand
#define TEST_FPSR_OP_V16_32( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
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TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \
LI(testreg, fcsr_val) ; \
csrw fcsr, testreg ; \
vsetivli x0, 1, e16, m1, ta, ma ; \
vfmv.s.f v1, freg ; \
inst v2, v1 ; \
vsetivli x0, 1, e32, m1, ta, ma ; \
vfmv.f.s destreg, v2 ; \
csrr flagreg, fcsr ; \
)

//Tests for floating-point instructions with a single register operand
//This variant does not take the rm field and set it while writing the instruction
#define TEST_FPSR_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
#define TEST_FPSR_OP_NRM_V32_16( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg) ;\
li testreg, fcsr_val; csrw fcsr, testreg ;\
inst destreg, freg ;\
vsetivli x0, 1, e32, m1, ta, ma ; \
vfmv.s.f v1, freg ; \
vsetivli x0, 1, e16, m1, ta, ma ; \
inst v2, v1 ; \
vfmv.f.s destreg, v2 ; \
csrr flagreg, fcsr ;\
)

//Tests for floating-point instructions with a single register operand
//This variant does not take the rm field and set it while writing the instruction
#define TEST_FPSR_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg) ; \
li testreg, fcsr_val; csrw fcsr, testreg ; \
inst destreg, freg ; \
csrr flagreg, fcsr ; \
)

//Tests for floating-point instructions with a single register operand and integer destination register
#define TEST_FPID_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg,load_instr) \
TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \
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