Updated the file with respect to Zhinx instructions

riscv_ctg/env/arch_test.h

@@ -111,6 +111,11 @@
   #define FSREG SREG
   #define FREGWIDTH 8
   #define FLEN 64
+#elif ZHINX==1
+  #define FLREG lw
+  #define FSREG sw
+  #define FREGWIDTH 4
+  #define FLEN 32
 #endif
 
 #if FLEN>XLEN

riscv_ctg/generator.py

@@ -260,7 +260,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx
 
 
         is_nan_box = False
-        is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x for x in opnode['isa']])
+        is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zhinx' in x for x in opnode['isa']])
         is_sgn_extd = True if (inxFlag and iflen <xlen) else False
 
         if is_fext:
@@ -812,6 +812,7 @@ def gen_inst(self,op_comb, val_comb, cgf):
                     for y in op_inds[i:]:
                         if op[y] == op[x]:
                             val[ind_dict[y]] = val[ind_dict[x]]
+
             if self.is_fext:
                 instr_dict.append(self.__fext_instr__(op,val))
             elif self.opcode == 'c.lui':
@@ -888,7 +889,7 @@ def eval_inst_coverage(coverpoints,instr):
             if (is_fp_instruction(insn)):
                 insn = "fadd.s"
             instr_obj = instructionObject(None, insn, None)
-            ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))})
+            ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen,'inxFlag': self.inxFlag, 'xlen': self.xlen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))})
 
             if ext_specific_vars is not None:
                 var_dict.update(ext_specific_vars)

riscv_ctg/helpers.py

@@ -78,7 +78,7 @@ def merge_fields_f(val_vars,cvp,flen,iflen,merge,inxFlag=False):
                     fdict[nan_var] = eval(match_obj.group(nan_var))
                 else:
                     fdict[nan_var] = (2**(flen-iflen))-1
-        elif sgn_extd:
+            elif sgn_extd:
                 sgn_var = 'rs{0}_sgn_prefix'.format(num_dict[var])
                 regex = val_regex.format(sgn_var.replace("_","\\_"),sgn_var)
                 match_obj = re.search(regex,cvp)

sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf

@@ -0,0 +1,188 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fadd_b1:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b1(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b2:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b2(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b3:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b3(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b4:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b4(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b5:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b5(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b7:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b7(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b8:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b8(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b10:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b10(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b11:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b11(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b12:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b12(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b13:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b13(flen,16, "fadd.h", 2,True)': 0

sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf

@@ -0,0 +1,92 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fcvt.w.h_b1:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fcvt.w.h: 0
+    rs1: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b1(flen,16, "fcvt.w.h", 1,True)': 0
+
+fcvt.w.h_b22:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fcvt.w.h: 0
+    rs1: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b22(flen,16, "fcvt.w.h", 1,True)': 0
+
+fcvt.w.h_b23:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fcvt.w.h: 0
+    rs1: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b23(flen,16, "fcvt.w.h", 1,True)': 0
+
+fcvt.w.h_b24:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fcvt.w.h: 0
+    rs1: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b24(flen,16, "fcvt.w.h", 1,True)': 0
+
+fcvt.w.h_b27:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fcvt.w.h: 0
+    rs1: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b27(flen,16, "fcvt.w.h", 1,True)': 0
+
+fcvt.w.h_b28:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fcvt.w.h: 0
+    rs1: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b28(flen,16, "fcvt.w.h", 1,True)': 0
+
+fcvt.w.h_b29:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fcvt.w.h: 0
+    rs1: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b29(flen,16, "fcvt.w.h", 1,True)': 0