updated the code for Zcf and Zcd extensions

riscv_ctg/data/imc.yaml

@@ -1890,3 +1890,85 @@ c.jalr:
     // opcode: c.jalr; op1:$rs1
     TEST_CJALR_OP($testreg, $rs1, $swreg, $offset)
 
+c.flw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0 
+  rd_op_data: *all_fregs
+  xlen: [32]
+  std_op:
+  isa: 
+    - IFC
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'clformat'
+  ea_align_data: '[0,1,2,3]'
+  rs1_val_data: '[0]'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
+  template: |-
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
+    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
+
+c.flwsp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_fregs
+  xlen: [32]
+  std_op:
+  isa: 
+    - IFC
+  formattype: 'ciformat'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'  
+  template: |-
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
+    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
+
+
+c.fsw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32]
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_fregs
+  isa: 
+    - IFC
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'csformat'
+  ea_align_data: '[0,1,2,3]'
+  rs1_val_data: '[0]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
+    // valreg: $valaddr_reg; valoffset: $val_offset
+    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
+
+
+c.fswsp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs2_op_data: *all_fregs
+  xlen: [32]
+  std_op:
+  isa: 
+    - IFC
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'cssformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
+    // valreg: $valaddr_reg; valoffset: $val_offset
+    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
+

riscv_ctg/data/template.yaml

@@ -4,6 +4,7 @@ metadata:
   all_fregs: &all_fregs "['f'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]"
   all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]"
   c_regs: &c_regs "['x'+str(x) for x in range(8,16)]"
+  c_fregs: &c_fregs "['x'+str(x) for x in range(8,16)]"
   pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
   rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]"
 

riscv_ctg/generator.py

@@ -260,7 +260,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx
 
 
         is_nan_box = False
-        is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x for x in opnode['isa']])
+        is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x for x in opnode['isa']])
         is_sgn_extd = True if (inxFlag and iflen <xlen) else False
 
         if is_fext:
@@ -281,7 +281,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx
         self.inxFlag = inxFlag
         self.is_sgn_extd = is_sgn_extd
 
-        if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw"]:
+        if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw","c.fld","c.flwsp","c.fswsp","c.fldsp","c.fsdsp"]:
             self.val_vars = self.val_vars + ['ea_align']
         self.template = opnode['template']
         self.opnode = opnode
@@ -818,7 +818,7 @@ def gen_inst(self,op_comb, val_comb, cgf):
                 instr_dict.append(self.__clui_instr__(op,val))
             elif self.opcode in ['c.beqz', 'c.bnez']:
                 instr_dict.append(self.__cb_instr__(op,val))
-            elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp']:
+            elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp','c.flwsp','c.fswsp','c.fldsp','c.fsdsp']:
                 if any([x == 'x2' for x in op]):
                     cont.append(val)
                 instr_dict.append(self.__cmemsp_instr__(op,val))
@@ -838,7 +838,7 @@ def gen_inst(self,op_comb, val_comb, cgf):
                 instr_dict.append(self.__clui_instr__(op,val))
             elif self.opcode in ['c.beqz', 'c.bnez','c.lbu','c.lhu','c.lh','c.sb','c.sh']:
                 instr_dict.append(self.__cb_instr__(op,val))
-            elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp']:
+            elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp','c.fsdsp','c.fswsp']:
                 instr_dict.append(self.__cmemsp_instr__(op,val))
             elif self.fmt == 'bformat' or self.opcode in ['c.j']:
                 instr_dict.append(self.__bfmt_instr__(op,val))

sample_cgfs/dataset.cgf

@@ -181,6 +181,16 @@ datasets:
     x14: 0
     x15: 0
 
+ c_fregs: &c_fregs
+    f8: 0
+    f9: 0
+    f10: 0
+    f11: 0
+    f12: 0
+    f13: 0
+    f14: 0
+    f15: 0
+
   all_regs_mx2: &all_regs_mx2
     x1: 0
     x3: 0

sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf

@@ -0,0 +1,65 @@
+c.flw:
+    config: 
+      - check ISA:=regex(.*I.*F.*C.*)
+    opcode: 
+      c.flw: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_fregs
+    val_comb:
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0
+
+c.flwsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*C.*)
+    opcode: 
+      c.flwsp: 0
+    rd: 
+      <<: *c_fregs
+    val_comb:
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0
+
+c.fsw:
+    config: 
+      - check ISA:=regex(.*I.*F.*C.*)
+    opcode: 
+      c.fsw: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_fregs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0
+
+c.fswsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*C.*)
+    opcode: 
+      c.fswsp: 0
+    rs2: 
+      <<: *c_fregs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0

sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf

@@ -0,0 +1,67 @@
+c.fld:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    mnemonics: 
+      c.fld: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_fregs
+    op_comb: 
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0
+
+c.fsd:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fsd: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_fregs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0
+
+c.fldsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fldsp: 0
+    rd: 
+      <<: *all_fregs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0
+
+c.fsdsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fsdsp: 0
+    rs2: 
+      <<: *all_fregs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0