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Merge pull request #22 from anku-anand/master
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updates for bitmnip instructions
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@neelgala
neelgala authored Jan 27, 2022
2 parents 8abfa33 + eae4230 commit 9284102
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Showing 6 changed files with 220 additions and 16 deletions.
4 changes: 4 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -2,6 +2,10 @@

This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

## [0.10.0] - 2022-01-27
- Added support for instructions from B extension.
- Bug fix for bgeu instruction.

## [0.9.0] - 2022-01-07
- Added support for P extension cover point generation and instruction decoding.
- Allowed an instruction to generate results in multiple registers.
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2 changes: 1 addition & 1 deletion riscv_isac/__init__.py
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Expand Up @@ -4,4 +4,4 @@

__author__ = """InCore Semiconductors Pvt Ltd"""
__email__ = '[email protected]'
__version__ = '0.9.0'
__version__ = '0.10.0'
14 changes: 9 additions & 5 deletions riscv_isac/coverage.py
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Expand Up @@ -23,23 +23,27 @@
from collections.abc import MutableMapping


unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd'\
unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd',\
'bgeu', 'bltu', 'sltiu', 'sltu','c.lw','c.ld','c.lwsp','c.ldsp',\
'c.sw','c.sd','c.swsp','c.sdsp','mulhu','divu','remu','divuw',\
'remuw','aes64ds','aes64dsm','aes64es','aes64esm','aes64ks2',\
'sha256sum0','sha256sum1','sha256sig0','sha256sig1','sha512sig0',\
'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig0l','sha512sig1h','sha512sig0h',\
'sha512sig1','sha512sum0','sha512sum1','sm3p0','sm3p1','aes64im',\
'sm4ed','sm4ks','ror','rol','rori','rorw','rolw','roriw','clmul','clmulh',\
'sm4ed','sm4ks','ror','rol','rori','rorw','rolw','roriw','clmul','clmulh','clmulr',\
'andn','orn','xnor','pack','packh','packu','packuw','packw',\
'xperm.n','xperm.b','grevi','aes64ks1i', 'shfli', 'unshfli', \
'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi']
'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\
'bset','zext.h','sext.h','sext.b','minu','maxu','orc.b','add.uw','sh1add.uw',\
'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\
'bclri','bexti','binvi','bseti']
unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\
'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\
'clmulh','andn','orn','xnor','pack','packh','packu','packuw','packw',\
'clmulh','clmulr','andn','orn','xnor','pack','packh','packu','packuw','packw',\
'xperm.n','xperm.b', 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi',\
'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h']
'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h','fsw',\
'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw']

class cross():

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212 changes: 204 additions & 8 deletions riscv_isac/plugins/internaldecoder.py
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Original file line number Diff line number Diff line change
Expand Up @@ -563,13 +563,20 @@ def arithi_ops(self, instrObj):
funct3 = (instr & self.FUNCT3_MASK) >> 12
funct4 = (instr & self.FUNCT4_MASK) >> 25
funct6 = (instr & self.FUNCT6_MASK) >> 26
funct7 = (instr >> 25)
rd = ((instr & self.RD_MASK) >> 7, 'x')
rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
rs2 = ((instr & self.RS2_MASK) >> 20, 'x')
rs3 = ((instr & self.RS3_MASK) >> 27, 'x')
imm = (instr >> 20)
imm_val = self.twos_comp(imm, 12)
bs = (instr & self.BS_MASK) >> 30
if self.arch == 'rv32':
sbi = (instr & 0xf8000000) >> 25
shamt = (instr & 0x1f00000) >> 20
elif self.arch == 'rv64':
sbi = (instr & 0xfc000000) >> 26
shamt = (instr & 0x3f00000) >> 20

instrObj.rd = rd
instrObj.rs1 = rs1
Expand All @@ -590,7 +597,27 @@ def arithi_ops(self, instrObj):
instrObj.instr_name = 'andi'

if funct3 == 0b001:
if funct6 == 0b000010:
if funct7 == 0b0000100:
if instrObj.arch == 'rv32':
instrObj.instr_name = 'zip'
instrObj.rs1= rs1
instrObj.rd = rd
elif sbi == 0b0100100 or sbi == 0b010010:
instrObj.rs1 = rs1
instrObj.rd = rd
instrObj.shamt = shamt
instrObj.instr_name = 'bclri'
elif sbi == 0b0110100 or sbi == 0b011010:
instrObj.rs1 = rs1
instrObj.rd = rd
instrObj.shamt = shamt
instrObj.instr_name = 'binvi'
elif sbi == 0b0010100 or sbi == 0b001010:
instrObj.rs1 = rs1
instrObj.rd = rd
instrObj.shamt = shamt
instrObj.instr_name = 'bseti'
elif funct6 == 0b000010:
imm = (instr & 0x03F00000)>>20
instrObj.rs1 = rs1
instrObj.rd = rd
Expand Down Expand Up @@ -660,6 +687,28 @@ def arithi_ops(self, instrObj):
instrObj.rs1 = rs1
instrObj.rd = rd
instrObj.imm = bs
elif funct4 == 0b10000:
if rs2[0] == 0b00000:
instrObj.instr_name = 'clz'
instrObj.rs1 = rs1
instrObj.rd = rd
elif rs2[0] == 0b00010:
instrObj.instr_name = 'cpop'
instrObj.rs1 = rs1
instrObj.rd = rd
elif rs2[0] == 0b00001:
instrObj.instr_name = 'ctz'
instrObj.rs1 = rs1
instrObj.rd = rd
elif rs2[0] == 0b00100:
instrObj.instr_name = 'sext.b'
instrObj.rs1 = rs1
instrObj.rd = rd
elif rs2[0] == 0b00101:
instrObj.instr_name = 'sext.h'
instrObj.rs1 = rs1
instrObj.rd = rd

else:
instrObj.instr_name = 'slli'
instrObj.imm = None
Expand All @@ -670,7 +719,29 @@ def arithi_ops(self, instrObj):
instrObj.shamt = shamt

if funct3 == 0b101:
if funct6 == 0b000010:
if funct7 == 0b0000100:
if instrObj.arch == 'rv32':
instrObj.instr_name = 'unzip'
instrObj.rs1= rs1
instrObj.rd = rd
elif (instr >> 20) == 0x6B8 or (instr >> 20) == 0x698 :
instrObj.instr_name = 'rev8'
instrObj.rs1 = rs1
instrObj.rd = rd
elif (instr >> 20) == 0x687:
instrObj.instr_name = 'brev8'
instrObj.rs1 = rs1
instrObj.rd = rd
elif (instr >> 20) == 0x287:
instrObj.instr_name = 'orc.b'
instrObj.rs1 = rs1
instrObj.rd = rd
elif sbi == 0b0100100 or sbi == 0b010010:
instrObj.rs1 = rs1
instrObj.rd = rd
instrObj.shamt = shamt
instrObj.instr_name = 'bexti'
elif funct6 == 0b000010:
imm = (instr & 0x03F00000)>>20
instrObj.rs1 = rs1
instrObj.rd = rd
Expand Down Expand Up @@ -1081,6 +1152,21 @@ def arith_ops(self, instrObj):
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0100100:
instrObj.instr_name = 'bclr'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0110100:
instrObj.instr_name = 'binv'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0010100:
instrObj.instr_name = 'bset'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
else:
instrObj.instr_name = 'sll'

Expand All @@ -1090,6 +1176,21 @@ def arith_ops(self, instrObj):
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
if funct7 == 0b0010000:
instrObj.instr_name = 'sh1add'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0000101:
instrObj.instr_name = 'clmulr'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0010100:
instrObj.instr_name = 'xperm4'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
else:
instrObj.instr_name = 'slt'

Expand All @@ -1109,10 +1210,31 @@ def arith_ops(self, instrObj):
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0000100:
instrObj.instr_name = 'pack'
if rs2[0] == 0b0:
instrObj.instr_name = 'zext.h'
instrObj.rs1 = rs1
instrObj.rd = rd
else:
instrObj.instr_name = 'pack'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0000101:
instrObj.instr_name = 'min'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0010000:
instrObj.instr_name = 'sh2add'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0010100:
instrObj.instr_name = 'xperm8'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd

# elif funct7 == 0b0100100:
# instrObj.instr_name = 'packu'
# instrObj.rs1 = rs1
Expand All @@ -1136,13 +1258,34 @@ def arith_ops(self, instrObj):
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0000101:
instrObj.instr_name = 'minu'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0100100:
instrObj.instr_name = 'bext'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd


if funct3 == 0b110:
if funct7 == 0b0100000:
instrObj.instr_name = 'orn'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0010000:
instrObj.instr_name = 'sh3add'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0000101:
instrObj.instr_name = 'max'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
else:
instrObj.instr_name = 'or'

Expand All @@ -1157,11 +1300,16 @@ def arith_ops(self, instrObj):
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0000101:
instrObj.instr_name = 'maxu'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
else:
instrObj.instr_name = 'and'

return instrObj

def fence_ops(self, instrObj):
instr = instrObj.instr
funct3 = (instr & self.FUNCT3_MASK) >> 12
Expand Down Expand Up @@ -1228,6 +1376,7 @@ def rv64i_arithi_ops(self, instrObj):

funct3 = (instr & self.FUNCT3_MASK) >> 12
funct7 = (instr >> 25)
funct7a = (instr >> 26) # for slli.uw
rd = ((instr & self.RD_MASK) >> 7, 'x')
rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
imm = ((instr & self.RS2_MASK) >> 20)
Expand All @@ -1245,8 +1394,28 @@ def rv64i_arithi_ops(self, instrObj):
instrObj.shamt = shamt

if funct3 == 0b001:
instrObj.instr_name = 'slliw'
if funct3 == 0b101:
if funct7a == 0b000010:
print("instr is slli.uw")
instrObj.instr_name = 'slli.uw'
instrObj.rs1 = rs1
instrObj.rd = rd
instrObj.shamt = imm
elif funct7 == 0b0110000:
if imm == 0b00000:
instrObj.instr_name = 'clzw'
instrObj.rs1 = rs1
instrObj.rd = rd
elif imm == 0b00001:
instrObj.instr_name = 'ctzw'
instrObj.rs1 = rs1
instrObj.rd = rd
elif imm == 0b00010:
instrObj.instr_name = 'cpopw'
instrObj.rs1 = rs1
instrObj.rd = rd
else:
instrObj.instr_name = 'slliw'
elif funct3 == 0b101:
if funct7 == 0b0110000:
instrObj.instr_name = 'roriw'
instrObj.rs1 = rs1
Expand Down Expand Up @@ -1307,6 +1476,8 @@ def rv64i_arith_ops(self, instrObj):
if funct3 == 0b000:
if funct7 == 0b0000000:
instrObj.instr_name = 'addw'
if funct7 == 0b0000100:
instrObj.instr_name = 'add.uw'
if funct7 == 0b0100000:
instrObj.instr_name = 'subw'

Expand All @@ -1319,9 +1490,26 @@ def rv64i_arith_ops(self, instrObj):
else:
instrObj.instr_name = 'sllw'

if funct3 == 0b010:
if funct7 == 0b0010000:
instrObj.instr_name = 'sh1add.uw'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd

if funct3 == 0b100:
if funct7 == 0b0000100:
instrObj.instr_name = 'packw'
if rs2[0] == 0b0:
instrObj.instr_name = 'zext.h'
instrObj.rs1 = rs1
instrObj.rd = rd
else:
instrObj.instr_name = 'packw'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0010000:
instrObj.instr_name = 'sh2add.uw'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd
Expand All @@ -1342,8 +1530,16 @@ def rv64i_arith_ops(self, instrObj):
instrObj.rs2 = rs2
instrObj.rd = rd

return instrObj
if funct3 == 0b110:
if funct7 == 0b0010000:
instrObj.instr_name = 'sh3add.uw'
instrObj.rs1 = rs1
instrObj.rs2 = rs2
instrObj.rd = rd


return instrObj

rv32a_instr_names = {
0b00010: 'lr.w',
0b00011: 'sc.w',
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2 changes: 1 addition & 1 deletion setup.cfg
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
[bumpversion]
current_version = 0.9.0
current_version = 0.10.0
commit = True
tag = True

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2 changes: 1 addition & 1 deletion setup.py
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ def read_requires():

setup(
name='riscv_isac',
version='0.9.0',
version='0.10.0',
description="RISC-V ISAC",
long_description=readme + '\n\n',
classifiers=[
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