Fixed avalon reads

The avalon master cocotb driver removes the read address after 1 clock
cycle and sets it to x or u. This screws up the read process of the
implemented corsair avalon master module interface by giving out x's on
the read port.
It is fixed by clocking in the address into an internal read address and
use that for the read process.

corsair/templates/amm2lb_verilog.j2

@@ -56,6 +56,7 @@ wire              ren;
 
   assign wstrb = byteenable;
   reg ren_int;
+  reg {{ range_decl(config['data_width'] - 1) }} raddr_int;
   {% set rst_type = config['register_reset']%}
   {%- if rst_type == 'async_pos' or rst_type == 'sync_pos' %}
       {% set rst_active = 1%}
@@ -78,6 +79,13 @@ wire              ren;
     end
   end
 
+  reg {{ range_decl(config['data_width'] - 1) }} raddr_int;
+  {{ always_begin(sig='raddr_int', width=config['data_width'], init=read_filler
+  )}} if (read) begin
+        raddr_int <= address;
+      end
+  end
+
   assign ren = ren_int;
 {% endmacro %}
 {{ amm_core() }}

corsair/templates/amm2lb_vhdl.j2

@@ -95,6 +95,7 @@ signal raddr  : std_logic_vector(ADDR_W-1 downto 0);
 signal ren    : std_logic;
     {% endif %}
 signal ren_int   : std_logic;
+signal raddr_int : std_logic_vector(ADDR_W-1 downto 0);
 {% endmacro %}
 {{ amm_signals() }}
 begin
@@ -120,8 +121,14 @@ wstrb <= byteenable;
     end if;
 {{ process_end() }}
 
+{{ process_begin("raddr_int", "(others=>'0')") }}
+    if (read = '1') then
+        raddr_int <= address;
+    end if;
+{{ process_end() }}
+
 ren <= ren_int;
 
 {% endmacro %}
 {{ amm_core() }}
-end arch_imp;
+end arch_imp;

corsair/templates/regmap_vhdl.j2

@@ -532,10 +532,10 @@ wready <= '1';
 {% set loop_ns = namespace(first_reg = True) %}
 {% for reg in rmap %}
     {% if loop_ns.first_reg %}
-        if raddr = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
+        if raddr_int = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
             rdata_ff <= {{ sig_csr_rdata(reg) }};
     {% else %}
-        elsif raddr = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
+        elsif raddr_int = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
             rdata_ff <= {{ sig_csr_rdata(reg) }};
     {% endif %}
     {% set loop_ns.first_reg = False %}