Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fixes output constraints for LOADFP instruction #170

Merged
merged 2 commits into from
May 15, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
41 changes: 40 additions & 1 deletion basic/tests/test_prover.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ use valida_alu_u32::lt::{Lt32Instruction, Lte32Instruction, Sle32Instruction, Sl
use valida_basic::BasicMachine;
use valida_cpu::{
BeqInstruction, BneInstruction, Imm32Instruction, JalInstruction, JalvInstruction,
MachineWithCpuChip, StopInstruction,
LoadFpInstruction, MachineWithCpuChip, StopInstruction,
};
use valida_machine::{
FixedAdviceProvider, Instruction, InstructionWord, Machine, MachineProof, Operands, ProgramROM,
Expand Down Expand Up @@ -378,6 +378,29 @@ fn signed_inequality_program<Val: PrimeField32 + TwoAdicField>() -> Vec<Instruct
program
}

fn loadfp_program<Val: PrimeField32 + TwoAdicField>() -> Vec<InstructionWord<i32>> {
let mut program = vec![];
// loadfp 4(fp), 0, 0, 0, 0
// loadfp 8(fp), 3, 0, 0, 0
// stop
program.extend([
InstructionWord {
opcode: <LoadFpInstruction as Instruction<BasicMachine<Val>, Val>>::OPCODE,
operands: Operands([4, 0, 0, 0, 0]),
},
InstructionWord {
opcode: <LoadFpInstruction as Instruction<BasicMachine<Val>, Val>>::OPCODE,
operands: Operands([8, 3, 0, 0, 0]),
},
InstructionWord {
opcode: <StopInstruction as Instruction<BasicMachine<Val>, Val>>::OPCODE,
operands: Operands::default(),
},
]);

program
}

fn prove_program(program: Vec<InstructionWord<i32>>) -> BasicMachine<BabyBear> {
let mut machine = BasicMachine::<Val>::default();
let rom = ProgramROM::new(program);
Expand Down Expand Up @@ -584,3 +607,19 @@ fn prove_signed_inequality() {
Word([0, 0, 0, 0]) // 0xFFFFFFFF < 1 (false)
);
}

#[test]
fn prove_loadfp() {
let program = loadfp_program::<BabyBear>();

let machine = prove_program(program);

assert_eq!(
*machine.mem().cells.get(&(0x1000 + 4)).unwrap(),
Word([0, 0, 16, 0]) // fp = 0x1000 = (0, 0, 16, 0)
);
assert_eq!(
*machine.mem().cells.get(&(0x1000 + 8)).unwrap(),
Word([0, 0, 16, 3]) // fp(3) = 0x1003 = (0, 0, 16, 0)
);
}
13 changes: 8 additions & 5 deletions cpu/src/stark.rs
Original file line number Diff line number Diff line change
Expand Up @@ -119,7 +119,7 @@ impl CpuChip {
)
.assert_one(local.read_1_used());
builder
.when(is_jal + is_left_imm_op)
.when(is_jal + is_left_imm_op + is_loadfp + is_imm32)
Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Here and below we add some missing cases to the memory channel constraints, asserting that the read channels are unused for IMM32 and LOADFP and that the write channel is unused for BEQ and BNE.

.assert_zero(local.read_1_used());

// Read (2)
Expand All @@ -130,7 +130,7 @@ impl CpuChip {
);
builder
.when(is_store)
.assert_eq(local.read_addr_2(), addr_b);
.assert_eq(local.read_addr_2(), addr_b.clone());
builder
.when(is_jalv + (AB::Expr::one() - is_imm_op) * is_bus_op)
.assert_eq(local.read_addr_2(), addr_c);
Expand All @@ -143,12 +143,12 @@ impl CpuChip {
)
.assert_one(local.read_2_used());
builder
.when(is_jal + is_imm_op * (is_beq + is_bne) + is_imm_op * is_bus_op)
.when(is_jal + is_imm_op * (is_beq + is_bne + is_bus_op) + is_loadfp + is_imm32)
.assert_zero(local.read_2_used());

// Write
builder
.when(is_load + is_jal + is_jalv + is_imm32 + is_bus_op)
.when(is_load + is_jal + is_jalv + is_imm32 + is_bus_op + is_loadfp)
.assert_eq(local.write_addr(), addr_a);
builder
.when(is_store)
Expand Down Expand Up @@ -183,10 +183,13 @@ impl CpuChip {
);
builder
.when(is_loadfp)
.assert_eq(local.fp, reduce::<AB>(base, local.write_value()));
.assert_eq(addr_b, reduce::<AB>(base, local.write_value()));
builder
.when(is_store + is_load + is_jal + is_jalv + is_imm32 + is_loadfp + is_bus_op)
.assert_one(local.write_used());
builder
.when(is_beq + is_bne)
.assert_zero(local.write_used());
}

fn eval_pc<AB>(
Expand Down
Loading