Test

[WIP] Synlig, new system-verilog tool integration #9907

Job	Run time
ODIN-II Basic Test	39m 6s
B: Building VtR (release, 0)	31m 51s
B: GCC 9 (Ubuntu Jammy - 22.04)	28m 53s
B: Building VtR (debug, 0)	31m 49s
F: C/C++	1m 39s
B: GCC 10 (Ubuntu Jammy - 22.04)	31m 53s
B: Building VtR (debug, 1)	31m 16s
Parmys Basic Test	31m 37s
F: Python	1m 46s
B: GCC 11 (Ubuntu Jammy - 22.04)	30m 55s
F: Python Lint	2m 19s
B: GCC 12 (Ubuntu Jammy - 22.04)	37m 37s
S: Basic	10m 6s
B: Clang 11 (Ubuntu Jammy - 22.04)	36m 2s
R: Basic	25m 26s
B: Clang 12 (Ubuntu Jammy - 22.04)	37m 18s
R: Basic with highest assertion level	32m 7s
B: Clang 13 (Ubuntu Jammy - 22.04)	36m 9s
U: C++ Unit Tests	7m 55s
R: Basic_odin	14m 16s
VQM2BLIF Basic Tests	7m 22s
B: Clang 14 (Ubuntu Jammy - 22.04)	36m 8s
R: Basic with NO_GRAPHICS	28m 34s
R: Basic with NO_SERVER	24m 42s
W: Check Compilation Warnings	7m 36s
R: Basic with CAPNPROTO disabled	18m 19s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	16m 9s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	17m 10s
R: Strong	12m 20s
R: Strong_odin	17m 47s
R: Valgrind Memory	13m 35s
Coverity Scan	1s
	11h 39m 43s

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