Test

[WIP] Synlig, new system-verilog tool integration #9908

Job	Run time
B: Building VtR (release, 0)	15m 29s
F: C/C++	1m 8s
B: Building VtR (debug, 0)	15m 30s
F: Python	1m 10s
ODIN-II Basic Test	37m 39s
B: Building VtR (debug, 1)	15m 19s
F: Python Lint	1m 48s
Parmys Basic Test	15m 18s
S: Basic	21m 51s
R: Basic	10m 21s
U: C++ Unit Tests	12m 48s
R: Basic with highest assertion level	11m 52s
W: Check Compilation Warnings	12m 41s
R: Basic_odin	10m 3s
R: Basic with NO_GRAPHICS	10m 0s
R: Basic with NO_SERVER	6m 56s
B: GCC 9 (Ubuntu Jammy - 22.04)	14m 59s
R: Basic with CAPNPROTO disabled	9m 17s
B: GCC 10 (Ubuntu Jammy - 22.04)	15m 24s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	10m 23s
B: GCC 11 (Ubuntu Jammy - 22.04)	15m 30s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	10m 23s
B: GCC 12 (Ubuntu Jammy - 22.04)	18m 10s
R: Strong	10m 11s
R: Strong_odin	16m 16s
B: Clang 11 (Ubuntu Jammy - 22.04)	1m 46s
R: Valgrind Memory	10m 22s
B: Clang 12 (Ubuntu Jammy - 22.04)	1m 23s
B: Clang 13 (Ubuntu Jammy - 22.04)	19m 37s
VQM2BLIF Basic Tests	15m 17s
B: Clang 14 (Ubuntu Jammy - 22.04)	20m 1s
Coverity Scan	0s
	6h 28m 52s

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