Test

[WIP] Synlig, new system-verilog tool integration #9909

Job	Run time
B: Building VtR (release, 0)	15m 21s
U: C++ Unit Tests	13m 7s
B: Building VtR (debug, 0)	15m 42s
F: C/C++	1m 3s
B: Building VtR (debug, 1)	16m 1s
F: Python	57s
W: Check Compilation Warnings	12m 12s
F: Python Lint	1m 40s
ODIN-II Basic Test	37m 40s
B: GCC 9 (Ubuntu Jammy - 22.04)	13m 58s
B: GCC 10 (Ubuntu Jammy - 22.04)	15m 26s
Parmys Basic Test	15m 39s
B: GCC 11 (Ubuntu Jammy - 22.04)	15m 25s
R: Basic	15m 1s
B: GCC 12 (Ubuntu Jammy - 22.04)	17m 50s
R: Basic with highest assertion level	15m 54s
B: Clang 11 (Ubuntu Jammy - 22.04)	1m 8s
S: Basic	21m 50s
R: Basic_odin	14m 46s
B: Clang 12 (Ubuntu Jammy - 22.04)	1m 9s
R: Basic with NO_GRAPHICS	14m 58s
B: Clang 13 (Ubuntu Jammy - 22.04)	20m 22s
R: Basic with NO_SERVER	7m 1s
VQM2BLIF Basic Tests	15m 37s
B: Clang 14 (Ubuntu Jammy - 22.04)	19m 24s
R: Basic with CAPNPROTO disabled	13m 54s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	10m 43s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	15m 25s
R: Strong	15m 23s
R: Strong_odin	12m 52s
R: Valgrind Memory	6m 34s
Coverity Scan	0s
	6h 54m 2s

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