Test

[WIP] Synlig, new system-verilog tool integration #9911

Job	Run time
B: Building VtR (release, 0)	15m 46s
F: C/C++	1m 29s
B: Building VtR (debug, 0)	15m 38s
F: Python	1m 0s
B: Building VtR (debug, 1)	15m 58s
F: Python Lint	1m 40s
Parmys Basic Test	16m 7s
R: Basic	14m 53s
R: Basic with highest assertion level	14m 37s
S: Basic	22s
R: Basic_odin	15m 11s
U: C++ Unit Tests	18s
R: Basic with NO_GRAPHICS	14m 47s
R: Basic with NO_SERVER	6m 47s
W: Check Compilation Warnings	2s
R: Basic with CAPNPROTO disabled	13m 53s
B: GCC 9 (Ubuntu Jammy - 22.04)	14m 17s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	7m 23s
B: GCC 10 (Ubuntu Jammy - 22.04)	15m 19s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	14m 50s
B: GCC 11 (Ubuntu Jammy - 22.04)	15m 26s
ODIN-II Basic Test	16m 6s
R: Strong	1m 45s
B: GCC 12 (Ubuntu Jammy - 22.04)	16m 15s
VQM2BLIF Basic Tests	16s
R: Strong_odin	1m 36s
B: Clang 11 (Ubuntu Jammy - 22.04)	1m 14s
R: Valgrind Memory	54s
B: Clang 12 (Ubuntu Jammy - 22.04)	1m 13s
B: Clang 13 (Ubuntu Jammy - 22.04)	16m 11s
B: Clang 14 (Ubuntu Jammy - 22.04)	16m 12s
Coverity Scan	1s
	4h 47m 26s

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