Test

[WIP] Synlig, new system-verilog tool integration #9917

Job	Run time
B: Building VtR (release, 0)	33m 3s
B: Building VtR (debug, 0)	34m 46s
F: C/C++	1m 52s
B: Building VtR (debug, 1)	31m 54s
F: Python	2m 18s
F: Python Lint	2m 36s
R: Basic	28m 14s
S: Basic	24m 31s
R: Basic with highest assertion level	30m 11s
R: Basic_odin	13m 29s
U: C++ Unit Tests	28m 29s
R: Basic with NO_GRAPHICS	27m 58s
W: Check Compilation Warnings	18m 53s
R: Basic with NO_SERVER	22m 53s
B: GCC 9 (Ubuntu Jammy - 22.04)	12m 14s
R: Basic with CAPNPROTO disabled	17m 10s
ODIN-II Basic Test	40m 59s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	26m 15s
B: GCC 10 (Ubuntu Jammy - 22.04)	13m 31s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	16m 54s
B: GCC 11 (Ubuntu Jammy - 22.04)	13m 41s
R: Strong	19m 38s
B: GCC 12 (Ubuntu Jammy - 22.04)	13m 19s
R: Strong_odin	19m 38s
Parmys Basic Test	32m 49s
R: Valgrind Memory	20m 22s
B: Clang 11 (Ubuntu Jammy - 22.04)	17m 44s
B: Clang 12 (Ubuntu Jammy - 22.04)	15m 38s
B: Clang 13 (Ubuntu Jammy - 22.04)	17m 11s
VQM2BLIF Basic Tests	11m 7s
B: Clang 14 (Ubuntu Jammy - 22.04)	13m 31s
Coverity Scan	1s
	10h 22m 49s

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