Test

[WIP] Synlig, new system-verilog tool integration #9918

Job	Run time
B: Building VtR (release, 0)	22m 51s
B: Building VtR (debug, 0)	22m 56s
B: Building VtR (debug, 1)	22m 53s
F: C/C++	1m 46s
ODIN-II Basic Test	22m 52s
F: Python	1m 56s
F: Python Lint	2m 14s
Parmys Basic Test	22m 54s
R: Basic	22m 51s
R: Basic with highest assertion level	21m 6s
S: Basic	22m 54s
U: C++ Unit Tests	22m 42s
R: Basic_odin	17m 44s
W: Check Compilation Warnings	22m 45s
R: Basic with NO_GRAPHICS	20m 43s
R: Basic with NO_SERVER	20m 35s
B: GCC 9 (Ubuntu Jammy - 22.04)	1s
VQM2BLIF Basic Tests	22m 55s
R: Basic with CAPNPROTO disabled	22m 30s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	17m 44s
B: GCC 10 (Ubuntu Jammy - 22.04)	1s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	19m 1s
B: GCC 11 (Ubuntu Jammy - 22.04)	1s
R: Strong	10m 1s
B: GCC 12 (Ubuntu Jammy - 22.04)	1s
R: Strong_odin	5m 1s
B: Clang 11 (Ubuntu Jammy - 22.04)	3m 36s
R: Valgrind Memory	5m 1s
B: Clang 12 (Ubuntu Jammy - 22.04)	1s
B: Clang 13 (Ubuntu Jammy - 22.04)	55s
B: Clang 14 (Ubuntu Jammy - 22.04)	1s
Coverity Scan	1s
	6h 38m 33s

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