Test

[WIP] Synlig, new system-verilog tool integration #9919

Job	Run time
F: C/C++	2m 0s
B: Building VtR (release, 0)	33m 0s
F: Python	1m 36s
B: Building VtR (debug, 0)	30m 32s
F: Python Lint	2m 40s
B: Building VtR (debug, 1)	32m 45s
S: Basic	24m 53s
R: Basic	28m 38s
U: C++ Unit Tests	26m 25s
R: Basic with highest assertion level	22m 17s
W: Check Compilation Warnings	14m 39s
R: Basic_odin	15m 48s
R: Basic with NO_GRAPHICS	24m 39s
B: GCC 9 (Ubuntu Jammy - 22.04)	29m 53s
R: Basic with NO_SERVER	31m 54s
ODIN-II Basic Test	40m 51s
B: GCC 10 (Ubuntu Jammy - 22.04)	31m 50s
R: Basic with CAPNPROTO disabled	25m 14s
Parmys Basic Test	31m 27s
B: GCC 11 (Ubuntu Jammy - 22.04)	31m 45s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	22m 31s
B: GCC 12 (Ubuntu Jammy - 22.04)	38m 44s
VQM2BLIF Basic Tests	25m 58s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	15m 24s
B: Clang 11 (Ubuntu Jammy - 22.04)	37m 0s
R: Strong	16m 36s
B: Clang 12 (Ubuntu Jammy - 22.04)	37m 27s
R: Strong_odin	19m 39s
B: Clang 13 (Ubuntu Jammy - 22.04)	36m 45s
R: Valgrind Memory	29m 7s
B: Clang 14 (Ubuntu Jammy - 22.04)	36m 45s
Coverity Scan	1s
	13h 18m 43s

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