Test

[WIP] Synlig, new system-verilog tool integration #9920

Job	Run time
F: C/C++	1m 36s
F: Python	1m 45s
F: Python Lint	2m 20s
ODIN-II Basic Test	25m 14s
Parmys Basic Test	25m 16s
B: Building VtR (release, 0)	25m 15s
B: Building VtR (debug, 0)	25m 15s
R: Basic	25m 13s
S: Basic	24m 19s
U: C++ Unit Tests	25m 3s
R: Basic with highest assertion level	25m 12s
B: Building VtR (debug, 1)	25m 14s
R: Basic_odin	18m 6s
VQM2BLIF Basic Tests	24m 19s
R: Basic with NO_GRAPHICS	25m 7s
W: Check Compilation Warnings	20m 0s
R: Basic with NO_SERVER	25m 14s
R: Basic with CAPNPROTO disabled	25m 14s
B: GCC 9 (Ubuntu Jammy - 22.04)	1s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	22m 44s
B: GCC 10 (Ubuntu Jammy - 22.04)	1s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	18m 8s
B: GCC 11 (Ubuntu Jammy - 22.04)	1s
R: Strong	23m 24s
B: GCC 12 (Ubuntu Jammy - 22.04)	1s
R: Strong_odin	22m 50s
B: Clang 11 (Ubuntu Jammy - 22.04)	6m 49s
R: Valgrind Memory	7m 1s
B: Clang 12 (Ubuntu Jammy - 22.04)	24s
B: Clang 13 (Ubuntu Jammy - 22.04)	23s
B: Clang 14 (Ubuntu Jammy - 22.04)	22s
Coverity Scan	1s
	7h 51m 52s

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