Test

[WIP] Synlig, new system-verilog tool integration #9923

Job	Run time
B: Building VtR (release, 0)	31m 48s
R: Basic	26m 52s
B: Building VtR (debug, 0)	28m 53s
Parmys Basic Test	25m 27s
R: Basic with highest assertion level	15m 36s
B: Building VtR (debug, 1)	26m 12s
R: Basic_odin	18m 12s
U: C++ Unit Tests	28m 46s
R: Basic with NO_GRAPHICS	11m 13s
W: Check Compilation Warnings	27m 44s
R: Basic with NO_SERVER	10m 1s
B: GCC 9 (Ubuntu Jammy - 22.04)	20m 57s
R: Basic with CAPNPROTO disabled	10m 56s
F: C/C++	1m 41s
B: GCC 10 (Ubuntu Jammy - 22.04)	31m 10s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	8m 50s
ODIN-II Basic Test	36m 40s
F: Python	1m 33s
B: GCC 11 (Ubuntu Jammy - 22.04)	30m 54s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	13m 19s
F: Python Lint	2m 9s
B: GCC 12 (Ubuntu Jammy - 22.04)	16m 31s
R: Strong	8m 53s
B: Clang 11 (Ubuntu Jammy - 22.04)	36m 51s
S: Basic	25m 17s
R: Strong_odin	7m 38s
B: Clang 12 (Ubuntu Jammy - 22.04)	37m 15s
VQM2BLIF Basic Tests	31m 57s
R: Valgrind Memory	7m 37s
B: Clang 13 (Ubuntu Jammy - 22.04)	37m 3s
B: Clang 14 (Ubuntu Jammy - 22.04)	36m 44s
Coverity Scan	1s
	10h 54m 40s

Provide feedback