Test

[WIP] Synlig, new system-verilog tool integration #9926

Job	Run time
U: C++ Unit Tests	21m 25s
F: C/C++	2m 12s
F: Python	1m 39s
B: Building VtR (release, 0)	17m 40s
F: Python Lint	2m 26s
B: GCC 9 (Ubuntu Jammy - 22.04)	23m 32s
ODIN-II Basic Test	41m 8s
B: Building VtR (debug, 0)	14m 14s
B: GCC 10 (Ubuntu Jammy - 22.04)	25m 8s
B: Building VtR (debug, 1)	14m 2s
Parmys Basic Test	28m 18s
R: Basic	15m 14s
B: GCC 11 (Ubuntu Jammy - 22.04)	19m 10s
S: Basic	26m 2s
R: Basic with highest assertion level	24m 24s
B: GCC 12 (Ubuntu Jammy - 22.04)	29m 53s
VQM2BLIF Basic Tests	18m 42s
R: Basic_odin	15m 7s
B: Clang 11 (Ubuntu Jammy - 22.04)	28m 9s
W: Check Compilation Warnings	15m 13s
R: Basic with NO_GRAPHICS	22m 3s
B: Clang 12 (Ubuntu Jammy - 22.04)	29m 41s
R: Basic with NO_SERVER	19m 9s
B: Clang 13 (Ubuntu Jammy - 22.04)	29m 19s
R: Basic with CAPNPROTO disabled	16m 29s
B: Clang 14 (Ubuntu Jammy - 22.04)	28m 2s
R: Basic with VTR_ENABLE_DEBUG_LOGGING	23m 35s
R: Basic_odin with VTR_ENABLE_DEBUG_LOGGING	17m 59s
R: Strong	31m 24s
R: Strong_odin	24m 14s
R: Valgrind Memory	28m 0s
Coverity Scan	23m 5s
	11h 16m 38s

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