VPR: interchange: add initial support for the interchange netlist frontend #1894
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Signed-off-by: Alessandro Comodi <[email protected]>
git-subtree-dir: libs/EXTERNAL/libinterchange git-subtree-split: 53e3feda4628e39e939ce8d2e4add72025809d42
libinterchange: Adding libs/EXTERNAL/libinterchange/ as an external git subtree from https://github.com/chipsalliance/fpga-interchange-schema.git main
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
This commit does the following: - options addition to read the interchange device and netlist and write the physical interchange. - basic support for the architecture reading: - Models - Device - Layout - Switches Signed-off-by: Alessandro Comodi <[email protected]> Co-authored-by: Maciej Dudek <[email protected]> Co-authored-by: Alessandro Comodi <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
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Description
This PR is a follow-up to #1893, and is based on top of it.
This PR adds the FPGA interchange netlist reading capability, as well as a very basic unit test that, for the time being is checking whether the netlist can be read without errors.
Motivation and Context
Alongside with the architecture reading, the netlist can also be expressed by means of the Interchange format.
How Has This Been Tested?
Basic unit test added to read in a test interchange netlist file.
Types of changes
Checklist: