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Updating k6_N10_40nm.xml arch and adding a sparse version; making more user friendly for teaching use #2454

Merged
merged 17 commits into from
Sep 6, 2024
Merged

Updating k6_N10_40nm.xml arch and adding a sparse version; making more user friendly for teaching use #2454

merged 17 commits into from
Sep 6, 2024

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vaughnbetz
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Updating k6_N10_40nm.xml and adding k6_N10_sparse_crossbar_40nm.xml. These architectures are now more heavily commented and suitable for work in a grad course (ECE 1756).

Description

I cut the logic block areas to something more reasonable for a simple architecture like this; the area numbers for the logic blocks and the local mux delays for the sparse architecture are based on coarse scaling / guessing so they aren't extremely accurate.

Removed some very complex comments, and added some more basic ones. Deleted dead code and comments in the arch files. Switched to per LUT input delays so we can demonstrate flat routing.

Motivation and Context

Useful for teaching (assignment 4) in ECE 1756.

How Has This Been Tested?

Tested with simple MCNC designs to show they work and get reasonable results.

Checklist:

  • All new and existing tests passed
  • [] Not done yet: should add a test to cover the sparse architecture.

Vaughn Betz added 2 commits November 28, 2023 19:06
Updating k6_N10_40nm.xml and adding k6_N10_sparse_crossbar_40nm.xml. …
896f75f 
…These architectures are now more heavily commented and suitable for work in a grad course (ECE 1756). I cut the logic block areas to something more reasonable for a simple architecture like this; the area numbers for the logic blocks and the local mux delays for the sparse architecture are based on coarse scaling / guessing so they aren't extremely accurate.
Updating vtr_reg_nightly1/vpr_mcnc_equiv golden results to lower logi…
bf664cd 
…c block area due to arch file update for 1756
@vaughnbetz
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@amin1377 : if you can take over updating golden results so we can land this it would be good. I don't know when I'll get back to it given the tasks in front of it ....

@vaughnbetz
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2024-08-16T14:26:26.5733988Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail]
2024-08-16T14:26:26.5734837Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5736376Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc vpr_status Task value 'success' does not match golden '-1'
2024-08-16T14:26:26.5737824Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5739274Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc error Task value 'None' does not match golden '-1'
2024-08-16T14:26:26.5740587Z �[32;1m14:26:26�[0m |
2024-08-16T14:26:26.5741397Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail]
2024-08-16T14:26:26.5742245Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5743787Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc vpr_status Task value 'success' does not match golden '-1'
2024-08-16T14:26:26.5745204Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5746651Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc error Task value 'None' does not match golden '-1'
2024-08-16T14:26:26.5748069Z �[32;1m14:26:26�[0m |
2024-08-16T14:26:26.5748824Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail]
2024-08-16T14:26:26.5749676Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5751185Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc vpr_status Task value 'success' does not match golden '-1'
2024-08-16T14:26:26.5752678Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5754193Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc error Task value 'None' does not match golden '-1'
2024-08-16T14:26:26.5755554Z �[32;1m14:26:26�[0m |
2024-08-16T14:26:26.5756365Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay...[Fail]
2024-08-16T14:26:26.5757266Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5759228Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 215576.0
2024-08-16T14:26:26.5761184Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5763325Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 107788.0
2024-08-16T14:26:26.5765393Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_buf...[Pass]
2024-08-16T14:26:26.5766252Z �[32;1m14:26:26�[0m |
2024-08-16T14:26:26.5767066Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail]
2024-08-16T14:26:26.5767921Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5769899Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0
2024-08-16T14:26:26.5771721Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5773677Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0
2024-08-16T14:26:26.5775423Z �[32;1m14:26:26�[0m |
2024-08-16T14:26:26.5776187Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail]
2024-08-16T14:26:26.5777157Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5779099Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0
2024-08-16T14:26:26.5780853Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5782856Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0
2024-08-16T14:26:26.5784641Z �[32;1m14:26:26�[0m |
2024-08-16T14:26:26.5785407Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail]
2024-08-16T14:26:26.5786264Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5788137Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_total relative value 0.3339887945771287 outside of range [0.8,1.3] and not equal to golden value: 9108090.0
2024-08-16T14:26:26.5789862Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5791726Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 8353570.0
2024-08-16T14:26:26.5793471Z �[32;1m14:26:26�[0m |
2024-08-16T14:26:26.5794233Z �[32;1m14:26:26�[0m | regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail]
2024-08-16T14:26:26.5795088Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5797061Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_total relative value 0.3339887945771287 outside of range [0.8,1.3] and not equal to golden value: 9108090.0
2024-08-16T14:26:26.5798793Z �[32;1m14:26:26�[0m | [Fail]
2024-08-16T14:26:26.5800677Z �[32;1m14:26:26�[0m | timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 8353570.0

Looks like we need to update golden (above from nightly_test_3).
The clock aliases result is odd -- it seems the golden results don't expect success? If you can take a look at the clock_aliases test to make sure the new result is indeed a pass (flow completed) then we can just update golden for it too (not sure how we got a golden result that was failure).

@vaughnbetz
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Thanks @amin1377 ! Getting close.
Looks like just a golden update for the strong_clock_aliases test in vtr_reg_strong:

2024-08-23T00:13:33.8415229Z regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail]
2024-08-23T00:13:33.8415614Z [Fail]
2024-08-23T00:13:33.8416438Z timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc vpr_status Task value 'success' does not match golden '-1'
2024-08-23T00:13:33.8417210Z [Fail]
2024-08-23T00:13:33.8417940Z timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc error Task value 'None' does not match golden '-1'
2024-08-23T00:13:33.8418611Z
2024-08-23T00:13:33.8418805Z regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail]
2024-08-23T00:13:33.8419186Z [Fail]
2024-08-23T00:13:33.8419994Z timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc vpr_status Task value 'success' does not match golden '-1'
2024-08-23T00:13:33.8420779Z [Fail]
2024-08-23T00:13:33.8421543Z timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc error Task value 'None' does not match golden '-1'
2024-08-23T00:13:33.8422228Z
2024-08-23T00:13:33.8422614Z regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail]
2024-08-23T00:13:33.8423010Z [Fail]
2024-08-23T00:13:33.8423825Z timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc vpr_status Task value 'success' does not match golden '-1'
2024-08-23T00:13:33.8424619Z [Fail]
2024-08-23T00:13:33.8425382Z timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc error Task value 'None' does not match golden '-1'
2024-08-23T00:13:33.8426069Z
2024-08-23T00:13:33.8426300Z regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay...[Fail]
2024-08-23T00:13:33.8426733Z [Fail]
2024-08-23T00:13:33.8427875Z timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 215576.0
2024-08-23T00:13:33.8429004Z [Fail]
2024-08-23T00:13:33.8430124Z timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 107788.0
2024-08-23T00:13:33.8431291Z regression_tests/vtr_reg_strong/strong_clock_buf...[Pass]
2024-08-23T00:13:33.8431590Z
2024-08-23T00:13:33.8431793Z regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail]
2024-08-23T00:13:33.8432572Z [Fail]
2024-08-23T00:13:33.8433706Z timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0
2024-08-23T00:13:33.8434748Z [Fail]
2024-08-23T00:13:33.8435846Z timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0
2024-08-23T00:13:33.8436800Z
2024-08-23T00:13:33.8437006Z regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail]
2024-08-23T00:13:33.8437406Z [Fail]
2024-08-23T00:13:33.8438501Z timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0
2024-08-23T00:13:33.8439727Z [Fail]
2024-08-23T00:13:33.8440816Z timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0
2024-08-23T00:13:33.8441775Z
2024-08-23T00:13:33.8441971Z regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail]
2024-08-23T00:13:33.8442376Z [Fail]
2024-08-23T00:13:33.8443454Z timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_total relative value 0.3339887945771287 outside of range [0.8,1.3] and not equal to golden value: 9108090.0
2024-08-23T00:13:33.8444457Z [Fail]
2024-08-23T00:13:33.8445529Z timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 8353570.0
2024-08-23T00:13:33.8446459Z
2024-08-23T00:13:33.8446659Z regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail]
2024-08-23T00:13:33.8447048Z [Fail]
2024-08-23T00:13:33.8448118Z timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_total relative value 0.3339887945771287 outside of range [0.8,1.3] and not equal to golden value: 9108090.0
2024-08-23T00:13:33.8449120Z [Fail]
2024-08-23T00:13:33.8450186Z timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 8353570.0

@amin1377
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@vaughnbetz, the CI tests are finally green!

@amin1377
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amin1377 commented Sep 6, 2024

@vaughnbetz : I think we can merge this PR.

@vaughnbetz
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Thanks @amin1377 !

@vaughnbetz vaughnbetz merged commit a342b67 into master Sep 6, 2024
52 checks passed
@vaughnbetz vaughnbetz deleted the update_1756_archs branch September 6, 2024 22:24
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@vaughnbetz @amin1377