Updating k6_N10_40nm.xml arch and adding a sparse version; making more user friendly for teaching use

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt

@@ -1,4 +1,4 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	  0.22	  vpr	  56.38 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57728	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  17.5 MiB	  0.00	  20	  56.4 MiB	  0.00	  0.00	  2.18276	  0	  0	  2.18276	  0.01	  1.8962e-05	  1.3558e-05	  0.000245191	  0.000217063	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.01	  0.00299768	  0.00243283	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.00	  0.00	  0.000845095	  0.000768207	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	  0.27	  vpr	  56.31 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57664	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  17.5 MiB	  0.00	  20	  56.3 MiB	  0.00	  0.00	  2.18276	  0	  0	  2.18276	  0.01	  1.974e-05	  1.4252e-05	  0.000246873	  0.0002189	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.01	  0.00244336	  0.00196958	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.00	  0.00	  0.000719288	  0.000650332	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	  0.29	  vpr	  56.34 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57696	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  17.5 MiB	  0.01	  20	  56.3 MiB	  0.00	  0.00	  2.18276	  0	  0	  2.18276	  0.01	  1.9454e-05	  1.4029e-05	  0.000249021	  0.000220542	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.01	  0.00264112	  0.00212219	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.00	  0.00	  0.000734735	  0.000667954	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	0.33	vpr	57.89 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59280	1	4	28	32	2	10	9	4	4	16	clb	auto	19.6 MiB	0.01	20	27	15	8	4	57.9 MiB	0.00	0.00	2.44626	0	0	2.44626	0.02	6.522e-05	5.8807e-05	0.000520276	0.000480282	8	12	5	72000	72000	5593.62	349.601	0.03	0.00762819	0.00638476	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00235121	0.00216168	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	0.32	vpr	57.76 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59144	1	4	28	32	2	10	9	4	4	16	clb	auto	19.5 MiB	0.01	20	27	15	8	4	57.8 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	7.6909e-05	6.9134e-05	0.000530933	0.000491554	8	12	5	72000	72000	5593.62	349.601	0.03	0.00769087	0.00644081	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00237431	0.00218377	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	0.32	vpr	57.91 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59304	1	4	28	32	2	10	9	4	4	16	clb	auto	19.6 MiB	0.01	20	27	15	8	4	57.9 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	5.6889e-05	5.0331e-05	0.000476198	0.000438042	8	12	5	72000	72000	5593.62	349.601	0.03	0.00727055	0.00604445	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00234916	0.00215934	

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt

@@ -1,2 +1,2 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- timing/k6_N10_40nm.xml	  clock_set_delay_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	  0.21	  vpr	  56.37 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  2	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57720	  2	  2	  22	  24	  2	  4	  6	  4	  4	  16	  clb	  auto	  18.1 MiB	  0.00	  4	  56.4 MiB	  0.00	  0.00	  1.293	  0	  0	  1.293	  0.01	  1.7316e-05	  1.2051e-05	  0.000172483	  0.000143849	  6	  6	  1	  215576	  107788	  3924.73	  245.296	  0.00	  0.000640147	  0.000558617	  9	  3	  5	  5	  233	  128	  1.293	  1.293	  0	  0	  0	  0	  5503.53	  343.971	  0.00	  0.00	  0.000444617	  0.000393194	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	0.30	vpr	57.82 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59208	2	2	22	24	2	4	6	4	4	16	clb	auto	19.5 MiB	0.01	4	15	2	10	3	57.8 MiB	0.00	0.00	1.297	0	0	1.297	0.01	4.3769e-05	3.8064e-05	0.000324999	0.000293005	4	6	2	72000	36000	2827.54	176.721	0.01	0.00228834	0.0020767	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.00	0.00	0.00	-1	-1	0.00	0.00162095	0.00152882