-
Notifications
You must be signed in to change notification settings - Fork 6.7k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
General fix for MSPI drivers and Apollo3p mspi feature update #81762
base: main
Are you sure you want to change the base?
General fix for MSPI drivers and Apollo3p mspi feature update #81762
Conversation
The following west manifest projects have changed revision in this Pull Request:
⛔ DNM label due to: 1 impostor SHA Note: This message is automatically posted and updated by the Manifest GitHub Action. |
970a5e9
to
b0e390a
Compare
drivers/flash/flash_mspi_atxp032.c
Outdated
@@ -745,7 +754,7 @@ static int flash_mspi_atxp032_read_jedec_id(const struct device *flash, uint8_t | |||
{ | |||
struct flash_mspi_atxp032_data *data = flash->data; | |||
|
|||
id = &data->jedec_id; | |||
id = (uint8_t *)&data->jedec_id; |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I do not think this is correct, as the flash_read_jedec_id expects ID to be copied from what is read on device to buffer pointed by the id, but the buffer is specified by function as 3 byte (which is wrong anyway), and here it will overflow if ID is longer and also there is a question whether byte order is not changed on assignment?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Yeah, your are right.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
atxp032@0: SFDP v 1.7 AP fc with 4 PH
PH0: ff00 rev 1.7: 20 DW @ 28
Summary of BFP content:
DTR Clocking supported
Addressing: 4-Byte only
4-KiBy erase: uniform
Support 1-1-1
Flash density: 16777216 bytes
ET1: instr 20h for 4096 By; typ 144 ms, max 288 ms
ET2: instr 52h for 32768 By; typ 1152 ms, max 2304 ms
ET3: instr D8h for 65536 By; typ 2304 ms, max 4608 ms
Chip erase: typ 16384 ms, max 65536 ms
Byte program: type 12 + 12 * B us, max 48 + 48 * B us
Page program: typ 2048 us, max 8192 us
Page program size: 256 By
Suspend: B0h ; Resume: D0h
DPD: Enter B9h, exit ABh ; delay 8000 ns ; poll 0x3d
HOLD or RESET Disable: unsupported
QER: 0
0-4-4 Mode: not supported4-4-4 Mode sequences: enable 0x00 ; disable 0x0
4-byte addressing support: enter 0x40, exit 0x000
Soft Reset and Rescue Sequence support: 0x10
Status Register 1 support: 0x02
size = <134217728> bits;
sfdp-bfp = [
fd 20 8c ff ff ff ff 07 00 00 00 00 00 00 00 00
ee ff ff ff ff ff 00 00 ff ff 00 00 0c 20 0f 52
10 d8 00 00 80 42 46 01 81 ff 5a ff 20 61 06 44
d0 b0 d0 b0 f7 a7 d5 5c 00 00 00 ff 82 10 00 40
00 00 00 00 00 00 fc 01 21 00 10 00 00 00 42 62
];
PH1: ff05 rev 1.0: 5 DW @ 78
sfdp-ff05 = [
0c 0b 00 80 71 71 65 65 00 e4 94 dc 00 00 00 00
0c 57 24 00
];
PH2: ff87 rev 1.0: 28 DW @ 8c
sfdp-ff87 = [
00 00 00 00 80 00 00 00 08 d1 ff c7 08 d1 ff c7
00 05 c4 80 00 05 c4 81 00 05 c4 a5 00 05 c4 a5
71 65 03 d0 00 00 00 00 9c 00 00 00 88 23 59 9a
00 00 00 86 00 00 00 00 00 00 00 00 71 65 02 93
00 00 00 00 71 65 02 97 00 00 06 01 00 00 00 00
88 02 71 04 00 00 00 06 00 00 00 00 71 65 01 d6
71 65 01 d4 00 00 00 00 71 65 01 d0 00 00 38 05
];
PH3: ff0a rev 1.0: 4 DW @ d4
sfdp-ff0a = [
00 00 06 01 00 00 00 00 88 02 71 04 00 00 00 06
];
jedec-id = [1f a9 00];
5435c3c
to
6ca2b9d
Compare
@@ -31,7 +31,7 @@ LOG_MODULE_REGISTER(flash_mspi_atxp032, CONFIG_FLASH_LOG_LEVEL); | |||
#define NOR_WRITE_SIZE 1 | |||
#define NOR_ERASE_VALUE 0xff | |||
|
|||
#define ATXP032_VENDOR_ID 0x43 | |||
#define ATXP032_VENDOR_ID 0x1F |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
6ca2b9d
to
505d24f
Compare
Standarlized transfer priority and add a medium level. Signed-off-by: Swift Tian <[email protected]>
The example now takes necessary information from the device tree and print better transfer status. Signed-off-by: Swift Tian <[email protected]>
1. Moved ambiq specific macro to mspi_ambiq header. 2. Always fill rx&tx dummy settings regardless of transfer direction. 3. Add the CONFIG_MSPI_* macro for optional features. 4. Fixed the ID read process. Signed-off-by: Swift Tian <[email protected]>
505d24f
to
5338b19
Compare
1. Use the newly introduced am_hal_mspi_cq_scatter_xfer api 2. Remove async PIO support 3. Use separate AM_HAL_MSPI_REQ_SCRAMB_CONFIG instead of am_hal_mspi_device_configure 4. Add MSPI_DEVICE_CONFIG_RX_DUMMY & MSPI_DEVICE_CONFIG_TX_DUMMY support and bug fix. 5. Unblock sync dma transcieve. Signed-off-by: Swift Tian <[email protected]>
Add the flash_mspi_atxp032 driver to the example and verified that flash_mspi_atxp032_read_sfdp is working as expected. Signed-off-by: Swift Tian <[email protected]>
5338b19
to
9d14596
Compare
Updates for the common files
Ambiq specific update:
Introduce the
am_hal_mspi_cq_scatter_xfer
api with three modes(STREAM, NORMAL, LOOP) that can dynamically set transfer related settings in command queue.Tests:
\zephyr\tests\drivers\mspi\api
\zephyr\tests\drivers\mspi\flash
\zephyr\samples\drivers\jesd216
\zephyr\samples\drivers\memc
\zephyr\samples\drivers\mspi\mspi_async
\zephyr\samples\drivers\mspi\mspi_flash