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General fix for MSPI drivers and Apollo3p mspi feature update #81762

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General fix for MSPI drivers and Apollo3p mspi feature update #81762

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1764249
drivers: mspi: standarlized transfer priority
swift-tk Nov 22, 2024
8f3b5ae
samples: mspi: improve the mspi_async example
swift-tk Nov 22, 2024
cc6f9d1
drivers: mspi: shroud controller specifics and fix potential issue
swift-tk Nov 22, 2024
4175f02
drivers: mspi: feature updates for ambiq mspi controller
swift-tk Nov 22, 2024
c6e81b9
samples: jesd216: add atxp032 flash to example
swift-tk Nov 22, 2024
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46 changes: 25 additions & 21 deletions drivers/flash/flash_mspi_atxp032.c
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Original file line number Diff line number Diff line change
Expand Up @@ -124,6 +124,7 @@ static int flash_mspi_atxp032_command_write(const struct device *flash, uint8_t
data->trans.async = false;
data->trans.xfer_mode = MSPI_PIO;
data->trans.tx_dummy = tx_dummy;
data->trans.rx_dummy = data->dev_cfg.rx_dummy;
data->trans.cmd_length = 1;
data->trans.addr_length = addr_len;
data->trans.hold_ce = false;
Expand Down Expand Up @@ -155,6 +156,7 @@ static int flash_mspi_atxp032_command_read(const struct device *flash, uint8_t c

data->trans.async = false;
data->trans.xfer_mode = MSPI_PIO;
data->trans.tx_dummy = data->dev_cfg.tx_dummy;
data->trans.rx_dummy = rx_dummy;
data->trans.cmd_length = 1;
data->trans.addr_length = addr_len;
Expand Down Expand Up @@ -261,7 +263,7 @@ static int flash_mspi_atxp032_get_vendor_id(const struct device *flash, uint8_t
ret = flash_mspi_atxp032_command_read(flash, SPI_NOR_CMD_RDID, 0, 0, 0, buffer, 11);
*vendor_id = buffer[7];

data->jedec_id = (buffer[7] << 16) | (buffer[8] << 8) | buffer[9];
memcpy(&data->jedec_id, buffer + 7, 3);

return ret;
}
Expand Down Expand Up @@ -326,10 +328,11 @@ static int flash_mspi_atxp032_page_program(const struct device *flash, off_t off
data->trans.async = false;
data->trans.xfer_mode = MSPI_DMA;
data->trans.tx_dummy = data->dev_cfg.tx_dummy;
data->trans.rx_dummy = data->dev_cfg.rx_dummy;
data->trans.cmd_length = data->dev_cfg.cmd_length;
data->trans.addr_length = data->dev_cfg.addr_length;
data->trans.hold_ce = false;
data->trans.priority = 1;
data->trans.priority = MSPI_XFER_PRIORITY_MEDIUM;
data->trans.packets = &data->packet;
data->trans.num_packet = 1;
data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE;
Expand Down Expand Up @@ -375,6 +378,7 @@ static int flash_mspi_atxp032_busy_wait(const struct device *flash)
return ret;
}
LOG_DBG("status: 0x%x", status);
k_sleep(K_MSEC(1));
} while (status & SPI_NOR_WIP_BIT);

if (data->dev_cfg.io_mode != MSPI_IO_MODE_SINGLE) {
Expand Down Expand Up @@ -407,11 +411,12 @@ static int flash_mspi_atxp032_read(const struct device *flash, off_t offset, voi

data->trans.async = false;
data->trans.xfer_mode = MSPI_DMA;
data->trans.tx_dummy = data->dev_cfg.tx_dummy;
data->trans.rx_dummy = data->dev_cfg.rx_dummy;
data->trans.cmd_length = data->dev_cfg.cmd_length;
data->trans.addr_length = data->dev_cfg.addr_length;
data->trans.hold_ce = false;
data->trans.priority = 1;
data->trans.priority = MSPI_XFER_PRIORITY_MEDIUM;
data->trans.packets = &data->packet;
data->trans.num_packet = 1;
data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE;
Expand Down Expand Up @@ -681,21 +686,25 @@ static int flash_mspi_atxp032_init(const struct device *flash)
}
data->timing_cfg = cfg->tar_timing_cfg;

#if CONFIG_MSPI_XIP
if (cfg->tar_xip_cfg.enable) {
if (mspi_xip_config(cfg->bus, &cfg->dev_id, &cfg->tar_xip_cfg)) {
LOG_ERR("Failed to enable XIP/%u", __LINE__);
return -EIO;
}
data->xip_cfg = cfg->tar_xip_cfg;
}
#endif /* CONFIG_MSPI_XIP */

#if CONFIG_MSPI_SCRAMBLE
if (cfg->tar_scramble_cfg.enable) {
if (mspi_scramble_config(cfg->bus, &cfg->dev_id, &cfg->tar_scramble_cfg)) {
LOG_ERR("Failed to enable scrambling/%u", __LINE__);
return -EIO;
}
data->scramble_cfg = cfg->tar_scramble_cfg;
}
#endif /* MSPI_SCRAMBLE */

release(flash);

Expand All @@ -720,11 +729,12 @@ static int flash_mspi_atxp032_read_sfdp(const struct device *flash, off_t addr,

data->trans.async = false;
data->trans.xfer_mode = MSPI_DMA;
data->trans.tx_dummy = data->dev_cfg.tx_dummy;
data->trans.rx_dummy = 8;
data->trans.cmd_length = 1;
data->trans.addr_length = 3;
data->trans.hold_ce = false;
data->trans.priority = 1;
data->trans.priority = MSPI_XFER_PRIORITY_MEDIUM;
data->trans.packets = &data->packet;
data->trans.num_packet = 1;
data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE;
Expand All @@ -745,7 +755,7 @@ static int flash_mspi_atxp032_read_jedec_id(const struct device *flash, uint8_t
{
struct flash_mspi_atxp032_data *data = flash->data;

id = &data->jedec_id;
memcpy(id, &data->jedec_id, 3);
return 0;
}
#endif /* CONFIG_FLASH_JESD216_API */
Expand Down Expand Up @@ -808,23 +818,17 @@ static const struct flash_driver_api flash_mspi_atxp032_api = {
.time_to_break = 0, \
}

#if CONFIG_SOC_FAMILY_AMBIQ
#define MSPI_TIMING_CONFIG(n) \
{ \
.ui8WriteLatency = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 0), \
.ui8TurnAround = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 1), \
.bTxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 2), \
.bRxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 3), \
.bRxCap = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 4), \
.ui32TxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 5), \
.ui32RxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 6), \
.ui32RXDQSDelayEXT = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 7), \
}
#define MSPI_TIMING_CONFIG_MASK(n) DT_INST_PROP(n, ambiq_timing_config_mask)
#else
#define MSPI_TIMING_CONFIG(n)
#define MSPI_TIMING_CONFIG_MASK(n)
#endif
COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \
(MSPI_AMBIQ_TIMING_CONFIG(n)), ({})) \

#define MSPI_TIMING_CONFIG_MASK(n) \
COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \
(MSPI_AMBIQ_TIMING_CONFIG_MASK(n)), (MSPI_TIMING_PARAM_DUMMY)) \

#define MSPI_PORT(n) \
COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \
(MSPI_AMBIQ_PORT(n)), (0)) \

#define FLASH_MSPI_ATXP032(n) \
static const struct flash_mspi_atxp032_config flash_mspi_atxp032_config_##n = { \
Expand Down
4 changes: 2 additions & 2 deletions drivers/flash/flash_mspi_emul_device.c
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Original file line number Diff line number Diff line change
Expand Up @@ -215,7 +215,7 @@ static int flash_mspi_emul_write(const struct device *flash, off_t offset,
data->xfer.cmd_length = data->dev_cfg.cmd_length;
data->xfer.addr_length = data->dev_cfg.addr_length;
data->xfer.hold_ce = false;
data->xfer.priority = 1;
data->xfer.priority = MSPI_XFER_PRIORITY_MEDIUM;
data->xfer.packets = &data->packet;
data->xfer.num_packet = 1;
data->xfer.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE;
Expand Down Expand Up @@ -288,7 +288,7 @@ static int flash_mspi_emul_read(const struct device *flash, off_t offset,
data->xfer.cmd_length = data->dev_cfg.cmd_length;
data->xfer.addr_length = data->dev_cfg.addr_length;
data->xfer.hold_ce = false;
data->xfer.priority = 1;
data->xfer.priority = MSPI_XFER_PRIORITY_MEDIUM;
data->xfer.packets = &data->packet;
data->xfer.num_packet = 1;
data->xfer.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE;
Expand Down
37 changes: 16 additions & 21 deletions drivers/memc/memc_mspi_aps6404l.c
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Original file line number Diff line number Diff line change
Expand Up @@ -82,6 +82,7 @@ static int memc_mspi_aps6404l_command_write(const struct device *psram, uint8_t
data->trans.async = false;
data->trans.xfer_mode = MSPI_PIO;
data->trans.tx_dummy = 0;
data->trans.rx_dummy = data->dev_cfg.rx_dummy;
data->trans.cmd_length = 1;
data->trans.addr_length = 0;
data->trans.hold_ce = false;
Expand Down Expand Up @@ -118,6 +119,7 @@ static int memc_mspi_aps6404l_command_read(const struct device *psram, uint8_t c

data->trans.async = false;
data->trans.xfer_mode = MSPI_PIO;
data->trans.tx_dummy = data->dev_cfg.tx_dummy;
data->trans.rx_dummy = 0;
data->trans.cmd_length = 1;
data->trans.addr_length = 3;
Expand Down Expand Up @@ -393,8 +395,8 @@ static int memc_mspi_aps6404l_init(const struct device *psram)
.write_cmd = APS6404L_WRITE, \
.cmd_length = 1, \
.addr_length = 3, \
.mem_boundary = 1024, \
.time_to_break = 8, \
.mem_boundary = 1024, \
.time_to_break = 8, \
}

#define MSPI_DEVICE_CONFIG_QUAD(n) \
Expand All @@ -413,28 +415,21 @@ static int memc_mspi_aps6404l_init(const struct device *psram)
.write_cmd = APS6404L_QUAD_WRITE, \
.cmd_length = 1, \
.addr_length = 3, \
.mem_boundary = 1024, \
.time_to_break = 4, \
.mem_boundary = 1024, \
.time_to_break = 4, \
}

#if CONFIG_SOC_FAMILY_AMBIQ
#define MSPI_TIMING_CONFIG(n) \
{ \
.ui8WriteLatency = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 0), \
.ui8TurnAround = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 1), \
.bTxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 2), \
.bRxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 3), \
.bRxCap = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 4), \
.ui32TxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 5), \
.ui32RxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 6), \
.ui32RXDQSDelayEXT = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 7), \
}
#define MSPI_TIMING_CONFIG_MASK(n) DT_INST_PROP(n, ambiq_timing_config_mask)
#else
#define MSPI_TIMING_CONFIG(n) {}
#define MSPI_TIMING_CONFIG_MASK(n) MSPI_TIMING_PARAM_DUMMY
#define MSPI_PORT(n) 0
#endif
COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \
(MSPI_AMBIQ_TIMING_CONFIG(n)), ({})) \

#define MSPI_TIMING_CONFIG_MASK(n) \
COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \
(MSPI_AMBIQ_TIMING_CONFIG_MASK(n)), (MSPI_TIMING_PARAM_DUMMY)) \

#define MSPI_PORT(n) \
COND_CODE_1(CONFIG_SOC_FAMILY_AMBIQ, \
(MSPI_AMBIQ_PORT(n)), (0)) \

#define MEMC_MSPI_APS6404L(n) \
static const struct memc_mspi_aps6404l_config \
Expand Down
47 changes: 32 additions & 15 deletions drivers/mspi/mspi_ambiq.h
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,38 @@
}, \
}

#define MSPI_CQ_MAX_ENTRY MSPI0_CQCURIDX_CQCURIDX_Msk

#define TIMING_CFG_GET_RX_DUMMY(cfg) \
{ \
mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \
timing->ui8TurnAround; \
}

#define TIMING_CFG_SET_RX_DUMMY(cfg, num) \
{ \
mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \
timing->ui8TurnAround = num; \
}

#define MSPI_AMBIQ_TIMING_CONFIG(n) \
{ \
.ui8WriteLatency = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 0), \
.ui8TurnAround = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 1), \
.bTxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 2), \
.bRxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 3), \
.bRxCap = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 4), \
.ui32TxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 5), \
.ui32RxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 6), \
.ui32RXDQSDelayEXT = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 7), \
}

#define MSPI_AMBIQ_TIMING_CONFIG_MASK(n) DT_INST_PROP(n, ambiq_timing_config_mask)

#define MSPI_AMBIQ_PORT(n) \
((DT_REG_ADDR(DT_INST_BUS(n)) - MSPI0_BASE) / (DT_REG_SIZE(DT_INST_BUS(n)) * 4))


struct mspi_ambiq_timing_cfg {
uint8_t ui8WriteLatency;
uint8_t ui8TurnAround;
Expand All @@ -47,19 +79,4 @@ enum mspi_ambiq_timing_param {
MSPI_AMBIQ_SET_RXDQSDLYEXT = BIT(7),
};

#define MSPI_PORT(n) ((DT_REG_ADDR(DT_INST_BUS(n)) - MSPI0_BASE) / \
(DT_REG_SIZE(DT_INST_BUS(n)) * 4))

#define TIMING_CFG_GET_RX_DUMMY(cfg) \
{ \
mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \
timing->ui8TurnAround; \
}

#define TIMING_CFG_SET_RX_DUMMY(cfg, num) \
{ \
mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \
timing->ui8TurnAround = num; \
}

#endif
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