boards: st: nucleo_u5a5zj_q: enable USB HS #81774
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LL_APB2_GRP1_PERIPH_OTGPHYC is only provided by STM32F7 HAL layer, so add 'defined(CONFIG_SOC_SERIES_STM32F7X)' to support build on other platforms. Signed-off-by: Marcin Niestroj <[email protected]>
HSE is populated on Nucleo board, so it is better to use it due to increased accuracy. Additionally HSE will be reused to drive USB HS peripheral, which is not possible with MSIS. Signed-off-by: Marcin Niestroj <[email protected]>
Provide configuration for USB HS with embedded USB HS PHY. Disable USB_DC_STM32_CLOCK_CHECK, since USB PLL is expected to be sourced by 16MHz clock, instead of 48MHz. Signed-off-by: Marcin Niestroj <[email protected]>
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Thanks @mniestroj. Did you had a check to #80249 ? |
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No, I didn't. I will take a look at it and give it a try. Patches in this PR are from ~1.5 months ago, I just didn't have time to push them yet. I'll close this PR then. |
Thanks, don't hesitate to provide feedback in that PR! |
hi! please do, I'll go try rebasing my tree (although this week is thanksgiving week so things are a bit weird timing wise here) and see how things go. |
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Use HSE as PLL input source, to achieve clock increased accuracy. This allows to drive USB HS
peripheral clock, which is not possible with MSIS.
Provide configuration for USB HS with embedded USB HS PHY.
Tested with
west build -b nucleo_u5a5zj_q zephyr/samples/subsys/usb/cdc_acm: