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boards: st: nucleo_u5a5zj_q: enable USB HS #81774

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boards: st: nucleo_u5a5zj_q: enable USB HS #81774

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73245a8
drivers: usb: stm32: support 'st,stm32-usbphyc' on non-STM32F7
mniestroj Oct 8, 2024
af145ce
boards: st: nucleo_u5a5zj_q: use HSE as PLL input source
mniestroj Oct 8, 2024
1046eb4
boards: st: nucleo_u5a5zj_q: enable USB HS
mniestroj Oct 8, 2024
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5 changes: 5 additions & 0 deletions boards/st/nucleo_u5a5zj_q/Kconfig.defconfig
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Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
# Copyright (c) 2024 Marcin Niestroj
# SPDX-License-Identifier: Apache-2.0

configdefault USB_DC_STM32_CLOCK_CHECK
default n
2 changes: 2 additions & 0 deletions boards/st/nucleo_u5a5zj_q/doc/index.rst
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Expand Up @@ -204,6 +204,8 @@ The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware f
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB high-speed host/device bus |
+-----------+------------+-------------------------------------+


Other hardware features are not yet supported on this Zephyr port.
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9 changes: 4 additions & 5 deletions boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi
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Expand Up @@ -59,18 +59,17 @@
status = "okay";
};

&clk_msis {
&clk_hse {
status = "okay";
msi-range = <4>;
msi-pll-mode;
clock-frequency = <DT_FREQ_M(16)>;
};

&pll1 {
div-m = <1>;
mul-n = <80>;
mul-n = <20>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_msis>;
clocks = <&clk_hse>;
status = "okay";
};

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17 changes: 17 additions & 0 deletions boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts
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Expand Up @@ -32,6 +32,14 @@
volt-sensor0 = &vref1;
volt-sensor1 = &vbat4;
};

soc {
usbphyc: usbphyc@40017c00 {
compatible = "st,stm32-usbphyc";
reg = <0x40017c00 0x400>;
#phy-cells = <0>;
};
};
};

&flash0 {
Expand Down Expand Up @@ -74,3 +82,12 @@
&gpdma1 {
status = "okay";
};

zephyr_udc0: &usbotg_hs {
pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x0000c000>,
<&rcc STM32_SRC_HSE USBPHYC_SEL(0)>;
phys = <&usbphyc>;
status = "okay";
};
1 change: 1 addition & 0 deletions boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml
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Expand Up @@ -21,5 +21,6 @@ supported:
- backup_sram
- dma
- rtc
- usb_device
ram: 2450
flash: 4096
2 changes: 1 addition & 1 deletion drivers/usb/device/usb_dc_stm32.c
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Expand Up @@ -317,7 +317,7 @@ static int usb_dc_stm32_clock_enable(void)
LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
#endif

#if USB_OTG_HS_EMB_PHY
#if USB_OTG_HS_EMB_PHY && defined(CONFIG_SOC_SERIES_STM32F7X)
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
#endif
#endif /* USB_OTG_HS_ULPI_PHY */
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2 changes: 1 addition & 1 deletion drivers/usb/udc/udc_stm32.c
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Expand Up @@ -1076,7 +1076,7 @@ static int priv_clock_enable(void)
LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
#endif /* defined(CONFIG_SOC_SERIES_STM32H7X) */

#if USB_OTG_HS_EMB_PHY
#if USB_OTG_HS_EMB_PHY && defined(CONFIG_SOC_SERIES_STM32F7X)
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
#endif
#elif defined(CONFIG_SOC_SERIES_STM32H7X) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
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