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Vcs support #111

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merged 3 commits into from
Dec 21, 2024
Merged

Vcs support #111

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4a605e0
Add VCS support
Risto97 Dec 21, 2024
58cf568
Xcelium always use 64bit compilation
Risto97 Dec 21, 2024
3fc6682
Refactor simulation examples
Risto97 Dec 21, 2024
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4 changes: 4 additions & 0 deletions cmake/sim/cadence/xcelium.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,7 @@ function(xcelium IP_LIB)

## XMSIM command for running simulation
set(__xmsim_cmd xmsim
-64bit
${__lib_args}
${ARG_RUN_ARGS}
${LIBRARY}.${ARG_TOP_MODULE}
Expand Down Expand Up @@ -156,6 +157,7 @@ function(__xcelium_compile_lib IP_LIB)

set(DESCRIPTION "Compile Verilog and SV files of ${IP_LIB} with xcelium xmvlog in library ${LIBRARY}")
set(__xmvlog_cmd COMMAND xmvlog
-64bit
-sv
${ARG_XMVLOG_ARGS}
${SV_ARG_INCDIRS}
Expand All @@ -180,6 +182,7 @@ function(__xcelium_compile_lib IP_LIB)
endforeach()

set(__xmvhdl_cmd COMMAND xmvhdl
-64bit
${ARG_XMVHDL_ARGS}
${VHDL_ARG_INCDIRS}
${VHDL_CMP_DEFS_ARG}
Expand All @@ -189,6 +192,7 @@ function(__xcelium_compile_lib IP_LIB)
endif()

set(__xmelab_cmd COMMAND xmelab
-64bit
${ARG_XMELAB_ARGS}
worklib.${IP_NAME}
# -work ${OUTDIR}/${LIBRARY}
Expand Down
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