cost: correct cost for single bit internal cells

YosysHQ · May 7, 2024 · 4ea3112 · 4ea3112
1 parent e747d8b
commit 4ea3112
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/kernel/cost.cc b/kernel/cost.cc
@@ -135,8 +135,9 @@ unsigned int port_width_sum(RTLIL::Cell *cell)
 unsigned int CellCosts::get(RTLIL::Cell *cell)
 {
 
+	// simple 1-bit cells
 	if (gate_type_cost().count(cell->type))
-		return gate_type_cost().at(cell->type);
+		return 1;
 
 	if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
 		log_debug("%s is a module, recurse\n", cell->name.c_str());