Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

abc: Warn about replacing undef bits #3894

Merged
merged 1 commit into from
Sep 5, 2023
+10 −0
Merged

abc: Warn about replacing undef bits #3894

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 10 additions & 0 deletions passes/techmap/abc.cc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -127,10 +127,15 @@ bool clk_polarity, en_polarity, arst_polarity, srst_polarity;
RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
dict<int, std::string> pi_map, po_map;

int undef_bits_lost;

int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1)
{
assign_map.apply(bit);

if (bit == State::Sx)
undef_bits_lost++;

if (signal_map.count(bit) == 0) {
gate_t gate;
gate.id = signal_list.size();
Expand Down Expand Up @@ -880,10 +885,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
}
}

undef_bits_lost = 0;

had_init = false;
for (auto c : cells)
extract_cell(c, keepff);

if (undef_bits_lost)
log("Replacing %d occurrences of constant undef bits with constant zero bits\n", undef_bits_lost);

for (auto wire : module->wires()) {
if (wire->port_id > 0 || wire->get_bool_attribute(ID::keep))
mark_port(wire);
Expand Down