rtlil: Fix handling of connections on wire deletion

kernel/rtlil.cc

@@ -2157,17 +2157,10 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 		}
 
 		void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
-			log_assert(GetSize(lhs) == GetSize(rhs));
-			lhs.unpack();
-			rhs.unpack();
-			for (int i = 0; i < GetSize(lhs); i++) {
-				RTLIL::SigBit &lhs_bit = lhs.bits_[i];
-				RTLIL::SigBit &rhs_bit = rhs.bits_[i];
-				if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
-					lhs_bit = State::Sx;
-					rhs_bit = State::Sx;
-				}
-			}
+			// If a deleted wire occurs on the lhs or rhs we just remove that part
+			// of the assignment
+			lhs.remove2(*wires_p, &rhs);
+			rhs.remove2(*wires_p, &lhs);
 		}
 	};
 
@@ -4238,6 +4231,34 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
 	check();
 }
 
+void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other)
+{
+	if (other)
+		cover("kernel.rtlil.sigspec.remove_other");
+	else
+		cover("kernel.rtlil.sigspec.remove");
+
+	unpack();
+
+	if (other != NULL) {
+		log_assert(width_ == other->width_);
+		other->unpack();
+	}
+
+	for (int i = GetSize(bits_) - 1; i >= 0; i--) {
+		if (bits_[i].wire != NULL && pattern.count(bits_[i].wire)) {
+			bits_.erase(bits_.begin() + i);
+			width_--;
+			if (other != NULL) {
+				other->bits_.erase(other->bits_.begin() + i);
+				other->width_--;
+			}
+		}
+	}
+
+	check();
+}
+
 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
 {
 	if (other)

kernel/rtlil.h

@@ -924,6 +924,7 @@ struct RTLIL::SigSpec
 	void remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;
 	void remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
 	void remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
+	void remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);
 
 	void remove(int offset, int length = 1);
 	void remove_const();

tests/various/bug4082.ys

@@ -0,0 +1,8 @@
+read_verilog <<EOF
+module top;
+  wire a;
+  wire b;
+  assign a = b;
+endmodule
+EOF
+delete w:a