rtlil: Fix handling of connections on wire deletion

[povik]

Ought to fix #4082

The issue here is we replace removed wires in assignments with x-bits on both the LHS and RHS of the assignment. This triggers an assertion later on because we cannot assign to a constant.

[povik]

Removed assertion that's duplicated in SigSpec::remove2

[povik]

This change makes opt_clean get stuck on some input, e.g.

module \top
  wire $d
  wire width 2 $m$6

  wire output 1 \dout

  attribute \keep 1'1
  cell \some_cell \sc1
    connect \DATA { $m$6 [1] }
  end

  connect $m$6 [0] $d
end

[povik]

To address opt_clean getting stuck, I had to change what we do with the connection when a wire gets deleted: Now we don't create dummy wires, we remove the part of the assignment involving a deleted wire no matter if the deleted wire was on the LHS or the RHS.

[povik]

Rebased