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write_verilog: Making sure BUF cells are converted to expressions. #4163

Merged
merged 3 commits into from
Jan 30, 2024
Merged

write_verilog: Making sure BUF cells are converted to expressions. #4163

merged 3 commits into from
Jan 30, 2024

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QuantamHD
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These were previously not being converted correctly leading to yosys internal cells being written to my netlist.

@QuantamHD
write_verilog: Making sure BUF cells are converted to expressions.
d2a04cc 
These were previously not being converted correctly leading to yosys
internal cells being written to my netlist.

Signed-off-by: Ethan Mahintorabi <[email protected]>
@QuantamHD
fixes char* to string conversion issue
33fe2e4 
Signed-off-by: Ethan Mahintorabi <[email protected]>
povik
povik approved these changes Jan 26, 2024
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Looks good, the one comment is more of a call for discussion with anyone who wants to chime in

povik
povik requested changes Jan 29, 2024
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As is, this can generate invalid Verilog. Please remove the dump_attributes call then we can merge this.

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As is, this can generate invalid Verilog. Please remove the dump_attributes call then we can merge this.

Done.

@QuantamHD QuantamHD requested a review from povik January 30, 2024 00:57
povik
povik approved these changes Jan 30, 2024
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Thanks!

@povik povik merged commit 3537976 into YosysHQ:master Jan 30, 2024
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@QuantamHD QuantamHD deleted the fix_write_verilog branch January 30, 2024 15:38
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@QuantamHD @povik