Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Use cell edges data in check, improve messages #4184

Merged
merged 14 commits into from
Mar 25, 2024
Merged
Prev Previous commit
Next Next commit
check: Add coarse-grain false positive test
  • Loading branch information
povik committed Mar 11, 2024
commit 3eef6450f10b672c95864b1e35409febfd501ccd
12 changes: 12 additions & 0 deletions tests/various/check.ys
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
design -reset
read_verilog <<EOF
module top(input clk, input a, input b, output [9:0] x);
wire [9:0] ripple;
reg [9:0] prev_ripple = 9'b0;

always @(posedge clk) prev_ripple <= ripple;
assign ripple = {ripple[8:0], a} ^ prev_ripple; // only cyclic at the coarse-grain level
assign x = ripple[9] + b;
endmodule
EOF
check -assert