Use cell edges data in check, improve messages

[povik]

Partially obsoletes #4178.

Sample:

module top(y);
	output wire [7:0] y;
	wire f = ~y[0];
	assign y = &{f, 2'h0, {4{f}}, 1'h0};
endmodule

outputs

3. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: found logic loop in module top:
    cell $not$loop_test.v:3$1 ($not) source: loop_test.v:3.11-3.16
        A[0] --> Y[0]
    wire \f source: loop_test.v:3.7-3.8
    cell $reduce_and$loop_test.v:4$2 ($reduce_and) source: loop_test.v:4.13-4.37
        A[1] --> Y[0]
        A[2] --> Y[0]
        A[3] --> Y[0]
        ...
    wire \y [0] source: loop_test.v:2.20-2.21
Found and reported 1 problems.

[whitequark]

Oh, nice!

[povik]

Forced pushed to rebase, squash fixup

[povik]

Ideally we wouldn't need to special-case here, and instead could do a simple query to celltypes. Related: #4034

[povik]

TODO:

• add celledges rules for write ports, for symmetry
• add async reset -> data edge for clocked read ports

[povik]

We decided to add the asynchronous reset path for read ports, but in that case we should for consistence register the async reset paths on all FFs too, so that check commutes with memory_dff. I added that.

[povik]

I tested this out on the design attached to #4249:

3. Executing CHECK pass (checking for obvious problems).
Checking module cpu...
Checking module regfile...
Checking module alu...
Warning: found logic loop in module alu:
    cell $ternary$cpu_flat.v:98$351 ($mux) source: cpu_flat.v:98.129-98.155
        S[0] --> Y[1]
    wire $ternary$cpu_flat.v:98$351_Y [1] source: cpu_flat.v:98.129-98.155
    cell $ternary$cpu_flat.v:98$352 ($mux) source: cpu_flat.v:98.85-98.171
        B[1] --> Y[1]
    wire $ternary$cpu_flat.v:98$352_Y [1] source: cpu_flat.v:98.85-98.171
    cell $ternary$cpu_flat.v:98$354 ($mux) source: cpu_flat.v:98.49-98.172
        A[1] --> Y[1]
    wire $ternary$cpu_flat.v:98$354_Y [1] source: cpu_flat.v:98.49-98.172
    cell $ternary$cpu_flat.v:98$355 ($mux) source: cpu_flat.v:98.23-98.173
        A[1] --> Y[1]
    wire $ternary$cpu_flat.v:98$355_Y [1] source: cpu_flat.v:98.23-98.173
    cell $reduce_or$cpu_flat.v:102$391 ($reduce_or) source: cpu_flat.v:102.84-102.101
        A[1] --> Y[0]
    wire $reduce_or$cpu_flat.v:102$391_Y source: cpu_flat.v:102.84-102.101
    cell $ternary$cpu_flat.v:102$393 ($mux) source: cpu_flat.v:102.75-102.120
        B[0] --> Y[0]
    wire $ternary$cpu_flat.v:102$393_Y source: cpu_flat.v:102.75-102.120
    cell $logic_not$cpu_flat.v:102$394 ($logic_not) source: cpu_flat.v:102.73-102.121
        A[0] --> Y[0]
    wire $logic_not$cpu_flat.v:102$394_Y source: cpu_flat.v:102.73-102.121
    cell $ternary$cpu_flat.v:102$395 ($mux) source: cpu_flat.v:102.18-102.121
        A[0] --> Y[0]
    wire $ternary$cpu_flat.v:102$395_Y source: cpu_flat.v:102.18-102.121

...

Found and reported 16 problems.

I wonder whether we shouldn't omit some part of the information to make it more readable.

[povik]

With private wires omitted:

4. Executing CHECK pass (checking for obvious problems).
Checking module alu...
Warning: found logic loop in module alu:
    cell $ternary$cpu_flat.v:98$351 ($mux) source: cpu_flat.v:98.129-98.155
        S[0] --> Y[1]
    cell $ternary$cpu_flat.v:98$352 ($mux) source: cpu_flat.v:98.85-98.171
        B[1] --> Y[1]
    cell $ternary$cpu_flat.v:98$354 ($mux) source: cpu_flat.v:98.49-98.172
        A[1] --> Y[1]
    cell $ternary$cpu_flat.v:98$355 ($mux) source: cpu_flat.v:98.23-98.173
        A[1] --> Y[1]
    wire \result_reg [1] source: cpu_flat.v:17.22-17.32
    cell $reduce_or$cpu_flat.v:102$391 ($reduce_or) source: cpu_flat.v:102.84-102.101
        A[1] --> Y[0]
    cell $ternary$cpu_flat.v:102$393 ($mux) source: cpu_flat.v:102.75-102.120
        B[0] --> Y[0]
    cell $logic_not$cpu_flat.v:102$394 ($logic_not) source: cpu_flat.v:102.73-102.121
        A[0] --> Y[0]
    cell $ternary$cpu_flat.v:102$395 ($mux) source: cpu_flat.v:102.18-102.121
        A[0] --> Y[0]
    wire \z_out source: cpu_flat.v:27.15-27.20

[povik]

Forced pushed to pull in CI fix

[mmicko]

@povik could you please rebase this one ?

[povik]

@mmicko Done!

[mmicko]

Thanks @povik