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write_verilog: don't assign to a reg #4314

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Apr 3, 2024
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23 changes: 15 additions & 8 deletions backends/verilog/verilog_backend.cc
Original file line number Diff line number Diff line change
Expand Up @@ -2014,22 +2014,29 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec

void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
if (simple_lhs) {
bool all_chunks_wires = true;
for (auto &chunk : left.chunks())
if (chunk.is_wire() && reg_wires.count(chunk.wire->name))
all_chunks_wires = false;
if (!simple_lhs && all_chunks_wires) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, left);
f << stringf(" = ");
dump_sigspec(f, right);
f << stringf(";\n");
} else {
int offset = 0;
for (auto &chunk : left.chunks()) {
f << stringf("%s" "assign ", indent.c_str());
if (chunk.is_wire() && reg_wires.count(chunk.wire->name))
f << stringf("%s" "always%s\n%s ", indent.c_str(), systemverilog ? "_comb" : " @*", indent.c_str());
else
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, chunk);
f << stringf(" = ");
dump_sigspec(f, right.extract(offset, GetSize(chunk)));
f << stringf(";\n");
offset += GetSize(chunk);
}
} else {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, left);
f << stringf(" = ");
dump_sigspec(f, right);
f << stringf(";\n");
}
}

Expand Down
1 change: 1 addition & 0 deletions tests/simple/.gitignore
Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@
*.log
*.out
*.err
4 changes: 4 additions & 0 deletions tests/verilog/.gitignore
Original file line number Diff line number Diff line change
@@ -1,6 +1,10 @@
/*.log
/*.out
/*.err
/run-test.mk
/const_arst.v
/const_sr.v
/doubleslash.v
/roundtrip_proc_1.v
/roundtrip_proc_2.v
/assign_to_reg.v
22 changes: 22 additions & 0 deletions tests/verilog/assign_to_reg.ys
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
# https://github.com/yosyshq/yosys/issues/2035

read_ilang <<END
module \top
wire width 1 input 0 \halfbrite
wire width 2 output 1 \r_on
process $1
assign \r_on [1:0] 2'00
assign \r_on [1:0] 2'11
switch \halfbrite [0]
case 1'1
assign \r_on [1] 1'0
end
end
end
END
proc_prune
write_verilog assign_to_reg.v
design -reset

logger -expect-no-warnings
read_verilog assign_to_reg.v
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