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Functional backend #4401

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75f5174
Add generic topological sort and SCC detection
jix Apr 15, 2024
5e874dd
kernel/log: Add log_str helper for custom log_* functions/overloads
jix Apr 15, 2024
71fbf0b
kernel/rtlil: Add `SigBit operator[](int offset)` to `SigChunk`
jix Apr 15, 2024
1f0ddf4
drivertools: Utility code for indexing and traversing signal drivers
jix Apr 15, 2024
0460a16
WIP temporary drivertools example
jix Apr 15, 2024
2971cf3
topo_scc: Add sources_first option
jix Apr 11, 2024
b21d9d2
ComputeGraph datatype for the upcoming functional backend
jix Apr 11, 2024
07907ad
fixup! drivertools: Utility code for indexing and traversing signal d…
jix Apr 17, 2024
8a30f03
fix bugs in drivertools
aiju May 1, 2024
d4e3430
add initial version of functional C++ backend
aiju May 1, 2024
e8f5101
add initial version of functional smtlib backend
aiju May 23, 2024
a852d0c
Some missing includes
RCoeurjoly May 24, 2024
596f6de
Move Driver* implementation to drivertools.cc
RCoeurjoly May 24, 2024
4828e8d
Include cassert
RCoeurjoly May 24, 2024
2eb24db
Created tests for functional C++ backend, comparing its VCD output to…
RCoeurjoly May 25, 2024
ad63997
Check vcdiff output
RCoeurjoly May 25, 2024
6644127
Test all files in verilog dir
RCoeurjoly May 25, 2024
59e6c94
Check the return code of yosys and of vcd_harness
RCoeurjoly May 25, 2024
83d98c5
Specify VCD names to dump
RCoeurjoly May 25, 2024
905db0a
Print type of error
RCoeurjoly May 25, 2024
7cbbcaf
Dump first state only after module is initialized
RCoeurjoly May 27, 2024
c18d99c
Implement and test $mul. Use return, not exit in tests
RCoeurjoly May 27, 2024
4bfb50e
vcdiff gives error output on stderr
RCoeurjoly May 28, 2024
44e073f
Compare with sim -sim-cmp, not vcdiff
RCoeurjoly May 28, 2024
1628ac3
Copy test to cxxrtl to not forget
RCoeurjoly May 28, 2024
4b5c366
Remove cxxrtl from functional backend C++ testing, using yosys sim -s…
RCoeurjoly May 28, 2024
89d9339
WIP
RCoeurjoly May 28, 2024
ec6c48b
Multi bit testing infrastructure works
RCoeurjoly May 28, 2024
f64c19b
Change permissions of verilog files
RCoeurjoly May 28, 2024
c0b8e6c
Rename verilog files for consistency
RCoeurjoly May 28, 2024
37d7175
Rename verilog files for consistency
RCoeurjoly May 28, 2024
94171a4
Add some 8 bit tests for functional C++ backend
RCoeurjoly May 28, 2024
1ce9a97
Initial, failing implementation of div and mod cells
RCoeurjoly May 28, 2024
cdf4b1f
Added Functional backend C++ tests to make test
RCoeurjoly May 28, 2024
b8dc9c5
Create vcd file from sim if -sim-cmp fails
RCoeurjoly May 28, 2024
54536af
Remove coverage
RCoeurjoly May 28, 2024
556c6f7
sim-gold instead of sim-cmp for x values
RCoeurjoly May 31, 2024
52cc2ae
Fix locale issue
RCoeurjoly Jun 1, 2024
77f3534
Simplify $mul CellSimplifier
RCoeurjoly Jun 4, 2024
b126370
WIP
RCoeurjoly Jun 4, 2024
da2b076
WIP
RCoeurjoly Jun 4, 2024
ea1edcb
WIP
RCoeurjoly Jun 4, 2024
83a8e5d
WIP
RCoeurjoly Jun 5, 2024
a543819
Testing against RTLIL
RCoeurjoly Jun 6, 2024
8cadb04
Move files
RCoeurjoly Jun 6, 2024
5929df2
WIP
RCoeurjoly Jun 6, 2024
6f38d5f
WIP
RCoeurjoly Jun 6, 2024
89f124e
Compile with C++17
RCoeurjoly Jun 6, 2024
3a9a55e
Set on unique types for variant
RCoeurjoly Jun 6, 2024
a4d5d9a
scope is gold, not my_module
RCoeurjoly Jun 6, 2024
fb6511b
´Print also successful files
RCoeurjoly Jun 6, 2024
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RCoeurjoly committed Jun 6, 2024
commit 8cadb047bb07dcf0a285e1db0c81b3086bc0900d
10 changes: 5 additions & 5 deletions tests/functional/single_cells/run-test.sh
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
#!/bin/bash

# Initialize an array to store the names of failing Verilog files and their failure types
# Initialize an array to store the names of failing RTLIL files and their failure types
declare -A failing_files

# Function to run the test on a given Verilog file
# Function to run the test on a given RTLIL file
run_test() {
# Define the common variable for the relative path
BASE_PATH="../../../"
Expand All @@ -13,7 +13,7 @@ run_test() {
# Extract the base name without extension
local base_name=$(basename "$verilog_file" .v)

# Run yosys to process each Verilog file
# Run yosys to process each RTLIL file
if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_functional_cxx my_module_functional_cxx.cc"; then
echo "Yosys processed $verilog_file successfully."

Expand All @@ -23,7 +23,7 @@ run_test() {
# Generate VCD files with base_name
if ./vcd_harness ${base_name}_functional_cxx.vcd; then

# Run yosys to process each Verilog file
# Run yosys to process each RTLIL file
if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then
echo "Yosys sim $verilog_file successfully."
else
Expand All @@ -44,7 +44,7 @@ run_test() {

# Main function to run all tests
run_all_tests() {
# Loop through all Verilog files in the verilog directory
# Loop through all RTLIL files in the verilog directory
for verilog_file in verilog/*.v; do
run_test "$verilog_file"
done
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