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Functional backend #4401

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75f5174
Add generic topological sort and SCC detection
jix Apr 15, 2024
5e874dd
kernel/log: Add log_str helper for custom log_* functions/overloads
jix Apr 15, 2024
71fbf0b
kernel/rtlil: Add `SigBit operator[](int offset)` to `SigChunk`
jix Apr 15, 2024
1f0ddf4
drivertools: Utility code for indexing and traversing signal drivers
jix Apr 15, 2024
0460a16
WIP temporary drivertools example
jix Apr 15, 2024
2971cf3
topo_scc: Add sources_first option
jix Apr 11, 2024
b21d9d2
ComputeGraph datatype for the upcoming functional backend
jix Apr 11, 2024
07907ad
fixup! drivertools: Utility code for indexing and traversing signal d…
jix Apr 17, 2024
8a30f03
fix bugs in drivertools
aiju May 1, 2024
d4e3430
add initial version of functional C++ backend
aiju May 1, 2024
e8f5101
add initial version of functional smtlib backend
aiju May 23, 2024
a852d0c
Some missing includes
RCoeurjoly May 24, 2024
596f6de
Move Driver* implementation to drivertools.cc
RCoeurjoly May 24, 2024
4828e8d
Include cassert
RCoeurjoly May 24, 2024
2eb24db
Created tests for functional C++ backend, comparing its VCD output to…
RCoeurjoly May 25, 2024
ad63997
Check vcdiff output
RCoeurjoly May 25, 2024
6644127
Test all files in verilog dir
RCoeurjoly May 25, 2024
59e6c94
Check the return code of yosys and of vcd_harness
RCoeurjoly May 25, 2024
83d98c5
Specify VCD names to dump
RCoeurjoly May 25, 2024
905db0a
Print type of error
RCoeurjoly May 25, 2024
7cbbcaf
Dump first state only after module is initialized
RCoeurjoly May 27, 2024
c18d99c
Implement and test $mul. Use return, not exit in tests
RCoeurjoly May 27, 2024
4bfb50e
vcdiff gives error output on stderr
RCoeurjoly May 28, 2024
44e073f
Compare with sim -sim-cmp, not vcdiff
RCoeurjoly May 28, 2024
1628ac3
Copy test to cxxrtl to not forget
RCoeurjoly May 28, 2024
4b5c366
Remove cxxrtl from functional backend C++ testing, using yosys sim -s…
RCoeurjoly May 28, 2024
89d9339
WIP
RCoeurjoly May 28, 2024
ec6c48b
Multi bit testing infrastructure works
RCoeurjoly May 28, 2024
f64c19b
Change permissions of verilog files
RCoeurjoly May 28, 2024
c0b8e6c
Rename verilog files for consistency
RCoeurjoly May 28, 2024
37d7175
Rename verilog files for consistency
RCoeurjoly May 28, 2024
94171a4
Add some 8 bit tests for functional C++ backend
RCoeurjoly May 28, 2024
1ce9a97
Initial, failing implementation of div and mod cells
RCoeurjoly May 28, 2024
cdf4b1f
Added Functional backend C++ tests to make test
RCoeurjoly May 28, 2024
b8dc9c5
Create vcd file from sim if -sim-cmp fails
RCoeurjoly May 28, 2024
54536af
Remove coverage
RCoeurjoly May 28, 2024
556c6f7
sim-gold instead of sim-cmp for x values
RCoeurjoly May 31, 2024
52cc2ae
Fix locale issue
RCoeurjoly Jun 1, 2024
77f3534
Simplify $mul CellSimplifier
RCoeurjoly Jun 4, 2024
b126370
WIP
RCoeurjoly Jun 4, 2024
da2b076
WIP
RCoeurjoly Jun 4, 2024
ea1edcb
WIP
RCoeurjoly Jun 4, 2024
83a8e5d
WIP
RCoeurjoly Jun 5, 2024
a543819
Testing against RTLIL
RCoeurjoly Jun 6, 2024
8cadb04
Move files
RCoeurjoly Jun 6, 2024
5929df2
WIP
RCoeurjoly Jun 6, 2024
6f38d5f
WIP
RCoeurjoly Jun 6, 2024
89f124e
Compile with C++17
RCoeurjoly Jun 6, 2024
3a9a55e
Set on unique types for variant
RCoeurjoly Jun 6, 2024
a4d5d9a
scope is gold, not my_module
RCoeurjoly Jun 6, 2024
fb6511b
´Print also successful files
RCoeurjoly Jun 6, 2024
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4 changes: 4 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -558,6 +558,7 @@ $(eval $(call add_include_file,kernel/celltypes.h))
$(eval $(call add_include_file,kernel/consteval.h))
$(eval $(call add_include_file,kernel/constids.inc))
$(eval $(call add_include_file,kernel/cost.h))
$(eval $(call add_include_file,kernel/drivertools.h))
$(eval $(call add_include_file,kernel/ff.h))
$(eval $(call add_include_file,kernel/ffinit.h))
$(eval $(call add_include_file,kernel/ffmerge.h))
Expand Down Expand Up @@ -598,6 +599,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
OBJS += kernel/binding.o
OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
OBJS += kernel/drivertools.o
ifeq ($(ENABLE_ZLIB),1)
OBJS += kernel/fstdata.o
endif
Expand Down Expand Up @@ -847,6 +849,8 @@ endif
+cd tests/xprop && bash run-test.sh $(SEEDOPT)
+cd tests/fmt && bash run-test.sh
+cd tests/cxxrtl && bash run-test.sh
+cd tests/functional/single_bit && bash run-test.sh
+cd tests/functional/multi_bit && bash run-test.sh
@echo ""
@echo " Passed \"make test\"."
@echo ""
Expand Down
32 changes: 32 additions & 0 deletions a.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
#include "sim.h"
struct my_module_Inputs {
Signal<1> b;
Signal<1> a;

template <typename T> void dump(T &out) {
out("b", b);
out("a", a);
}
};

struct my_module_Outputs {
Signal<1> sum;

template <typename T> void dump(T &out) {
out("sum", sum);
}
};

struct my_module_State {

template <typename T> void dump(T &out) {
}
};

void my_module(my_module_Inputs const &input, my_module_Outputs &output, my_module_State const &current_state, my_module_State &next_state)
{
Signal<1> b = input.b;
Signal<1> a = input.a;
Signal<1> $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y = $add(a, b); //
output.sum = $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y;
}
32 changes: 32 additions & 0 deletions add.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
#include "sim.h"
struct my_module_Inputs {
Signal<1> b;
Signal<1> a;

template <typename T> void dump(T &out) {
out("b", b);
out("a", a);
}
};

struct my_module_Outputs {
Signal<1> sum;

template <typename T> void dump(T &out) {
out("sum", sum);
}
};

struct my_module_State {

template <typename T> void dump(T &out) {
}
};

void my_module(my_module_Inputs const &input, my_module_Outputs &output, my_module_State const &current_state, my_module_State &next_state)
{
Signal<1> b = input.b;
Signal<1> a = input.a;
Signal<1> $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y = $add(a, b); //
output.sum = $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y;
}
Empty file added add.smt
Empty file.
22 changes: 22 additions & 0 deletions add.smt2
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
; SMT-LIBv2 description generated by Yosys 0.41+101 (git sha1 52cc2ae5c, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
; yosys-smt2-module my_module
(declare-sort |my_module_s| 0)
(declare-fun |my_module_is| (|my_module_s|) Bool)
(declare-fun |my_module#0| (|my_module_s|) (_ BitVec 1)) ; \a
(declare-fun |my_module#1| (|my_module_s|) (_ BitVec 1)) ; \b
(define-fun |my_module#2| ((state |my_module_s|)) (_ BitVec 1) (bvadd (|my_module#0| state) (|my_module#1| state))) ; $add$tests/functional/single_bit/verilog/my_module_add.v:7$1_Y
; yosys-smt2-output sum 1
(define-fun |my_module_n sum| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#2| state)) #b1))
; yosys-smt2-input b 1
; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": "b", "smtoffset": 0, "type": "input", "width": 1}
(define-fun |my_module_n b| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#1| state)) #b1))
; yosys-smt2-input a 1
; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": "a", "smtoffset": 0, "type": "input", "width": 1}
(define-fun |my_module_n a| ((state |my_module_s|)) Bool (= ((_ extract 0 0) (|my_module#0| state)) #b1))
(define-fun |my_module_a| ((state |my_module_s|)) Bool true)
(define-fun |my_module_u| ((state |my_module_s|)) Bool true)
(define-fun |my_module_i| ((state |my_module_s|)) Bool true)
(define-fun |my_module_h| ((state |my_module_s|)) Bool true)
(define-fun |my_module_t| ((state |my_module_s|) (next_state |my_module_s|)) Bool true) ; end of module my_module
; yosys-smt2-topmod my_module
; end of yosys output
Empty file added alternative_and.smt
Empty file.
32 changes: 32 additions & 0 deletions and.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
#include "sim.h"
struct my_module_Inputs {
Signal<1> b;
Signal<1> a;

template <typename T> void dump(T &out) {
out("b", b);
out("a", a);
}
};

struct my_module_Outputs {
Signal<1> sum;

template <typename T> void dump(T &out) {
out("sum", sum);
}
};

struct my_module_State {

template <typename T> void dump(T &out) {
}
};

void my_module(my_module_Inputs const &input, my_module_Outputs &output, my_module_State const &current_state, my_module_State &next_state)
{
Signal<1> b = input.b;
Signal<1> a = input.a;
Signal<1> $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y = $add(a, b); //
output.sum = $add$tests_functional_single_bit_verilog_my_module_add_v_7$1$_Y;
}
23 changes: 23 additions & 0 deletions and.smt
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
(declare-datatype my_module_inputs ((my_module_inputs
(my_module_inputs_b (_ BitVec 1))
(my_module_inputs_a (_ BitVec 1))
)))
(declare-datatype my_module_outputs ((my_module_outputs
(my_module_outputs_sum (_ BitVec 1))
)))
(declare-datatype my_module_state ((my_module_state
)))
(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y))))))
(define-fun my_module_step ((inputs my_module_inputs) (current_state my_module_state)) (Pair my_module_outputs my_module_state)
(let (((b (my_module_inputs_b inputs))))
(let (((a (my_module_inputs_a inputs))))
(let ((($add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y (bvadd a b))))
(pair
(my_module_outputs
$add$tests/functional/single_bit/verilog/my_module_add.v_7$1$_Y ; sum
)
(my_module_state
)
)
)))
)
4 changes: 4 additions & 0 deletions backends/functional/Makefile.inc
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
OBJS += backends/functional/cxx.o
# OBJS += backends/functional/smtlib.o
# OBJS += backends/functional/alternative_cxx.o
# OBJS += backends/functional/alternative_smtlib.o
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